LTC3765
19
3765fb
For more information www.linear.com/LTC3765
APPLICATIONS INFORMATION
When the NMOS is on, the magnetizing current and reflected
inductor current are both flowing through the NMOS. The
inductor current is generally much larger than the mag
-
netizing current, which makes the magnetizing current
difficult to measure directly. Therefore, when the NMOS
is on the LTC3765 internally replicates the magnetizing
current based on transformer core parameters, the voltage
on the I
SMAG
pin at the end of the previous reset cycle,
and the sensed input voltage on the RUN pin. The RUN
pin must be connected to a resistive divider from V
IN
to ground for proper operation of the Direct Flux Limit.
At the end of the reset cycle, the voltage on the I
SMAG
pin is sampled and held internally. This voltage is an ac-
curate measurement
of the magnetizing current. When
the NMOS turns on, an internal ramp proportional to the
RUN pin voltage divided by the R
CORE
resistor increases
the internal replicated magnetizing current. If this internal
voltage exceeds 1V (or V
CC
+ 1V for the alternative AG
configuration of Figure 7b), then the NMOS is turned off
to prevent core saturation.
When the NMOS is turned off due to a Direct Flux Limit, the
secondary-side switch node falls. The LTC3766 detects this
prematurely falling switch node and turns off the forward
gate to allow the transformer core to reset. This switch
node behavior is indistinguishable from a primary-side
shutdown; therefore, if the switch node falls prematurely
for 19 consecutive cycles, the LTC3766 concludes that a
primary-side shutdown has occurred and will fault.
Choose R
CORE
based on the RUN pin divider network and
the transformer core parameters:
R
CORE
=
R2
R1+ R2
B
MAX
• A
C
•N
P
0.030
– 2kΩ
where R1 and R2 comprise the divider network on the
RUN pin, with R1 from V
IN
to the RUN pin and R2 from
the RUN pin to ground. B
MAX
is typically 2700 gauss for
a transformer designed to operate at 2000 gauss, A
C
is
the area of the core in cm
2
, and N
P
is the number of turns
on the primary winding of the transformer.
The internal approximation of the magnetizing current is
linear, which is accurate if the transformer flux density is
kept sufficiently far from saturation. As the flux density
approaches saturation, the magnetizing inductance of
the transformer decreases and the magnetizing current
increases rapidly. Depending on the particular core proper
-
ties, it may be necessary to additionally decrease B
MAX
in
the equations above.
In a resonant reset application, the active clamp is re
-
placed by a single reset capacitor. In this configuration,
the transformer core is reset every cycle and is less likely
to saturate; however, the transformer can still saturate
during certain transient conditions. The Direct Flux Limit
can also be configured to prevent core saturation in this
application. Connect the R
MAG
sense resistor in series
with the ground side of the resonant reset capacitor and
use
the equation above for R
CORE
to prevent saturation
in a forward converter with resonant reset. The Direct
Flux Limit may be disabled by tying I
SMAG
to ground and
floating the R
CORE
pin; however, disabling the Direct Flux
Limit leaves the application circuit open to transformer
saturation and is not recommended.
Active Clamp Capacitor
The active clamp capacitor, C
CLAMP
, stores the average reset
voltage of the transformer over many cycles. The voltage on
the clamp capacitor is generated by the transformer core
reset current, and will intrinsically adjust to the optimal
reset voltage regardless of other parameters. The voltage
across the capacitor at full load is approximately given by:
V
CL
=
IN
2
V
IN
– 1.15 V
OUT
•N
P
/N
S
( )
N
P
/N
S
is the main transformer turns ratio. The factor of
1.15 accounts for typical losses and delays. When PG
and AG are low, the bottom side of the clamp capacitor is
grounded, placing the reset voltage V
CL
on the SWP node
in Figure 1. When PG and AG are high, the topside of the
capacitor is grounded, and the voltage on the bottom side
of the capacitor is –V
CL
. Therefore the voltage seen on the
