LTC3765
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APPLICATIONS INFORMATION
In many applications, the LTC3766 supply is initially biased
by this open-loop duty cycle ramp. The maximum duty
cycle that the LTC3765 can provide therefore dictates
whether the LTC3766 has adequate bias for start-up.
The maximum duty cycle is typically 70%; however, the
setting of the DELAY pin (t
DPG
) decreases the maximum
on-time. Therefore, the maximum duty cycle during start-
up is 70%-(t
DPG
f
SW
• 100%). Be sure to allow adequate
margin between this maximum duty cycle and the duty
cycle required to bias the LTC3766.
In some applications, the LTC3766 is biased from a peak
charge circuit from an auxiliary winding of the main trans
-
former. This
configuration is shown in Figure 6. Since
the
LTC3765 open-loop start-up powers both the peak
charge circuit and the output voltage, the primary design
constraint on the soft-start capacitor value is to ensure
that the output does not overvoltage before the LTC3766
has adequate bias to take control. A good rule of thumb
is to select the soft-start capacitor so that the LTC3766
has adequate supply voltage before the output voltage has
risen to half of its regulation point.
For the peak
charge circuit of Figure 6, choose the value of
C
PK
based on the capacitance required to bias the LTC3766.
Then choose the auxiliary winding turns ratio N
A
/N
P
to give
a peak charge voltage at minimum V
IN
of approximately
30% more than the required V
CC
of the LTC3766.
A lower bound on the primary-side soft-start capacitor
(C
SS
) value was previously calculated in the overcurrent
section to ensure that the overcurrent comparator does not
trip on start-up into a full load. The value should generally
be in the range of 10nF toF. Choosing too small of a
value for C
SS
could potentially charge the output voltage
too quickly at no load or cause an overcurrent trip when
starting into full load. Choosing too large a value will cre
-
ate additional delay in the start-up, during which time the
linear regulator will be providing the current to switch the
primary NMOS. Extremely long start-up times should be
avoided to avoid excessive power dissipation in the linear
regulator pass device. A value of 33nF is a good starting
point for most applications.
The soft-start capacitor value should be verified by compar
-
ing the time for the peak charge circuit to deliver adequate
bias
to the LTC3766 to the time that the output voltage rises
to half of its regulated value. The time until the LTC3766
receives bias and takes control can be approximated by:
t
BIAS
10
3
R
EQ
C
PK
C
SS
+ 150µs
where R
EQ
is the sum of R
PK
and the series resistance
of diode D
PK
.
The time for the output voltage to reach half of its regulated
value can then be estimated by the following equation,
where V
OUT
is the final regulated output voltage:
t
OUT
10
4
C
SS
2
V
OUT
/ 2
( )
2
L C
OUT
f
SW
V
IN(MIN)
N
S
/N
P
( )
2
1/3
Figure 6. Peak Charge Circuit for Biasing the LTC3766
in a Self-Starting Application
PG
N
P
N
S
N
A
V
OUT
V
IN
C
OUT
L
3765 F06
FG NMOS
BODY DIODE
SG NMOS
BODY DIODE
LTC3766 V
AUX
C
PK
D
PK
R
PK
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APPLICATIONS INFORMATION
The above equation assumes that there is no load cur-
rent, which is the worst-case condition for output voltage
rise.
If t
OUT
is less than t
BIAS
, then the soft-start capacitor
value should be increased. Note that these equations are
approximations and the actual times will vary somewhat
with circuit parameters.
Gate Drivers
The active clamp gate driver (AG) and the primary switch
gate driver (PG) arein-phase,” with a programmable
overlap time set by the DELAY pin. Traditionally in active
clamp drivers, the AG driver must be level-shifted as shown
in the circuit in Figure 7a to drive the active clamp PMOS
gate from approximately V
D
toV
CC
+ V
D
, where V
D
is
the forward voltage drop across the Schottky diode D
AG
.
A silicon diode can be used instead of a Schottky barrier
diode; however, the forward voltage of the diode does
subtract from the available gate drive of the active clamp
PMOS. This is particularly important at the minimum V
CC
UVLO falling threshold.
The resistor, R
AG
, ensures that the active clamp PMOS
is off when not being driven. The active clamp level-shift
circuit components can be chosen with few
constraints. The
time
constant formed by R
AG
and C
AG
should be designed
to be substantially longer than the switching period of the
controller. A 0.1µF capacitor for C
AG
and a 10k resistor for
R
AG
result in a 1ms time constant, which provides suf-
ficient margin
for the 75kHz to 500kHz frequency range
available in the LTC3766.
Alternatively, the active clamp PMOS source can be returned
to the V
CC
supply bypass capacitor, as shown in Figure7b.
In this configuration, the level-shift circuit comprised of
C
AG
, D
AG
and R
AG
is not needed. The AG output drives the
gate of the PMOS between V
CC
and ground.
Figure 7a. Traditional AG and PG Driver Configuration
Figure 7b. Alternative AG and PG Driver Configuration
3765 F07a
V
IN
PRIMARY
SWITCH
NMOS
ACTIVE
CLAMP
PMOS
PG
AG
MAIN
TRANSFORMER
C
CLAMP
I
SMAG
D
AG
C
AG
R
AG
C
SN
R
SN
R
MAG
3765 F07b
V
IN
PRIMARY
SWITCH
NMOS
ACTIVE
CLAMP
PMOS
PG
AG
V
CC
MAIN
TRANSFORMER
C
CLAMP
C
SN
R
SN
C
VCC
I
SMAG
R
MAG
Unlike the configuration in Figure 7a, the main transformer
leakage current spike and magnetizing current return to
the V
CC
bypass capacitor. The V
CC
capacitor should be
increased to prevent excessive ripple on the supply and
a low impedance plane should be used to route V
CC
. The
LTC3765
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APPLICATIONS INFORMATION
ripple on the V
CC
capacitor (C
VCC
) due to the magnetizing
current can be approximated by the following equation:
V
CC
=
V
OUT
N
P
/N
S
( )
6.8 C
VCC
L
MAG
f
SW
2
1–
V
OUT
N
P
/N
S
( )
V
IN(MAX)
In general, a 4.7µF capacitor is a good choice for most
application circuits when the active clamp current is
returned to V
CC
.
Direct Flux Limit
In active clamp forward converters, it is essential to es
-
tablish an accurate limit to the transformer flux density
in
order to avoid core saturation during load transients or
when starting up into a pre-biased output. Although the
active clamp technique provides a suitable reset voltage
during steady-state operation, the sudden increase in
duty cycle caused in response to a pre-bias output or a
load step can cause the transformer flux to accumulate
orwalk,” potentially leading to saturation. This occurs
because the reset voltage on the active clamp capacitor
cannot keep up with the rapidly changing duty cycle. This
effect is most pronounced at low input voltage, where the
voltage loop demands a greater increase in duty cycle due
to the lower voltage available to ramp up the current in
the output inductor.
The LTC3765 and LTC3766 implement a new unique system
for monitoring and directly limiting the flux accumulation in
the transformer core. During a reset cycle, when the active
clamp PMOS is on, the magnetizing
current is sensed by
a
resistor (R
MAG
) connected to the source of the PMOS.
The voltage across this resistor is sensed by the I
SMAG
pin. Both the traditional and alternative configurations for
the active clamp driver, shown previously in Figures 7a
and 7b, are supported. In the traditional configuration, if
the voltage on the I
SMAG
pin is less than –1V, the active
clamp PMOS is turned off. Similarly for the alternative
configuration of Figure 7b, if the voltage on the I
SMAG
pin
is less than (V
CC
– 1V), the active clamp PMOS is turned
off. The I
SMAG
pin therefore directly monitors and limits
the magnetizing current to prevent core saturation in the
negative direction.
Choose the magnetizing current sense resistor value to
limit the transformer saturation current (I
SAT
):
R
MAG
=
1V
I
SAT
where the saturation current is calculated from the maxi-
mum flux density (B
MAX
), area of the core in cm
2
(A
C
),
number of turns on the primary (N
P
), and typical magne-
tizing inductance
(L
MAG(TYP)
) from the following formula:
I
SAT
=
B
MAX
A
C
N
P
10
8
L
MAG(TYP)
For a transformer designed for 2000 gauss operating flux
density, which is typical for a ferrite core, set B
MAX
to 2700
gauss to keep sufficiently far from saturation over tempera-
ture. For
the
Pulse PA08xx series power transformers used
in the Typical Applications section, A
C
= 0.59cm
2
. For the
Pulse PA09xx series power transformers, A
C
= 0.81cm
2
.
Be sure to use the typical value for the magnetizing induc-
tance in
this formula. Using a minimum value for L
MAG
,
which is generally specified in transformer data sheets,
artificially limits the flux swing. In general, multiplying
the minimum value by 1.25 gives a good estimate for the
typical value.

LTC3765IMSE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Active Clamp For Cntr & Gate Drvr
Lifecycle:
New from this manufacturer.
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