RT9750
14
DS9750-00 March 2017www.richtek.com
©
Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Name Function Addr Reset
EVENT_1_MASK MASK 0x01 0x00
Bit Mode Name Reset Value Description
7 R/W VBUS_OVP_MASK 0
VBUS over-voltage fault mask.
0 – no mask. INT will toggle when VBUS_OVP_FLT bit
is set. (default)
1 – VBUS_OVP_FLT is masked. INT will not toggle
when VBUS_OVP_FLT bit is set.
6 R/W IBUS_REG_MASK 0
IBUS over-current fault mask.
0 – no mask. INT will toggle when IBUS_REG_FLT bit is
set. (default)
1 – IBUS_REG_FLT is masked. INT will not toggle
when IBUS_REG_FLT bit is set.
5 R/W VBAT_REG_MASK 0
VBAT over-voltage fault mask.
0 – no mask. INT will toggle when VBAT_REG_LDO bit
is set. (default)
1 – VBAT_REG_LDO is masked. INT will not toggle
when VBAT_REG_LDO bit is set.
4 R/W Reserved 0 Reserved
3 R/W VOUT_REG_MASK 0
VOUT over-voltage fault mask.
0 – no mask. INT will toggle when VOUT_REG_LDO bit
is set. (default)
1 – VOUT_REG_LDO is masked. INT will not toggle
when VOUT_REG_LDO bit is set.
2 R/W TBUS_OTP_MASK 0
VBUS over-temperature fault mask.
0 – no mask. INT will toggle when TBUS_OTP_FLT bit
is set. (default)
1 – TBUS_OTP_FLT is masked. INT will not toggle
when TBUS_OTP_FLT bit is set.
1 R/W TBAT_OTP_MASK 0
BAT over-temperature fault mask.
0 – no mask. INT will toggle when TBAT_OTP_FLT bit
is set. (default)
1 – TBAT_OTP_FLT is masked. INT will not toggle
when TBAT_OTP_FLT bit is set.
0 R/W IBUS_IREV_MASK 0
IBUS reverse current fault mask.
0 – no mask. INT will toggle when IBUS_REV_FLT bit is
set. (default)
1 – IBUS_REV_FLT is masked. INT will not toggle when
IBUS_REV_FLT bit is set.
