RT9750
7
DS9750-00 March 2017 www.richtek.com
©
Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Parameter Symbol Test Conditions Min Typ Max Unit
VBUS ADC Range
V
BUS_ADC_RAN
VDDA > 3V, 16 averages
1.5 -- 6.5 V
VBUS ADC Accuracy
V
BUS_ADC_ACC
15 -- 15 mV
IBUS ADC Range
I
BUS_ADC_RAN
VDDA > 3V, 16 averages
0 -- 7 A
IBUS ADC Accuracy
I
BUS_ADC_ACC
200
-- 200 mA
VOUT ADC Range
V
OUT_ADC_RAN
VDDA > 3V, 16 averages
1.5 -- 6.5 V
VOUT ADC Accuracy
V
OUT_ADC_ACC
15 -- 15 mV
VDROP ADC Range
V
DROP_ADC_RAN
VDDA > 3V, 16 averages
0 -- 1000 mV
VDROP ADC Accuracy
V
DROP_ADC_ACC
15 -- 15 mV
VBAT ADC Range
V
BAT_ADC_RAN
VDDA > 3V, 16 averages
2.5 -- 5 V
VBAT ADC Accuracy
V
BAT_ADC_ACC
15 -- 15 mV
TSVBUS ADC Range
V
TSVBUS_ADC_RAN
VDDA > 3V, 16 averages
0 -- 2.4 V
TSVBUS ADC Accuracy
V
TSVBUS_ADC_ACC
15 -- 15 mV
TSBAT ADC Range
V
TSBAT_ADC_RAN
VDDA > 3V, 16 averages
0 -- 2.4 V
TSBAT ADC Accuracy
V
TSBAT_ADC_ACC
15 -- 15 mV
Junction Thermal ADC
Range
T
JC_ADC_RAN
VDDA > 3V, 16 averages
0 -- 125 °C
Junction Thermal ADC
Accuracy
T
JC_ADC_ACC
3 -- 3 °C
I
2
C Interface
Serial-Clock Frequency f
SCL_I
2
C
(Note 5) 10 -- 1000 kHz
I
2
C Input Logic
Threshold
V
IH_I
2
C
Logic high 1.5 -- -- V
V
IL_I
2
C
Logic low -- -- 0.4 V
EN Input
EN Input Logic
Threshold
V
IH_EN
Logic high 1 -- -- V
V
IL_EN
Logic low -- -- 0.4 V
EN Pull Down Resistor R
PD_EN
On chip -- 500 -- k
Device turn-on delay
time after EN pull-high
-- -- 500 s
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θ
JA
is measured under natural convection (still air) at T
A
= 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Specification is guaranteed by design and/or correlation with statistical process control.
