RT9750
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Name Function Addr Reset
ADC_CTRL ADC_CTRL 0x07 0x8F
Bit Mode Name Reset Value Description
7 R/W TDIE_ADC_EN 1
Enable/disable TDIE_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
3 R/W ADC_EN 1
Enable/disable ADC
0 – Disable ADC
1 – Enable ADC (default)
2 R/W ADC_RATE 1
Sets ADC conversion rate
0 – 1-shot conversion
1 – Continuous conversion (default)
1 R/W ADC_AVG_EN 1
Enable/disable ADC measurement averaging
0 – Disable averaging (instantaneous measurement)
1 – Enable averaging (default)
0 R/W ADC_SAMPLES 1
Sets the number of samples to be taken for an ADC
conversion
0 – 8 samples taken for averaging
1 – 16 samples taken for averaging (default)
Name Function Addr Reset
CONTROL CONTROL 0x06 0x2A
Bit Mode Name Reset Value Description
7 R/W VDROP_OVP_EN 0
Enables VDROP_OVP protection
0 – Disable VDROP_OVP (default)
1 – Enable VDROP_OVP
6 R/W VDROP_ALM_EN 0
Enables VDROP_ALM alarm
0 – Disable VDROP_ALM (default)
1 – Enable VDROP_ALM
5 R/W Reserved 1 Reserved
4 R/W CHG_EN 0
Software bit for charge enable. This enables the Load
Switch. This bit will be set to ‘0’ if reset or any action of
FET turned off (STATUS register).
0 – Charge disabled (default)
1 – Charge enabled
[3:2] R/W WATCHDOG<1:0> 10
Watchdog timer setting. R/W any register will clear the
watchdog timer. FET must turn off after watchdog timer
out.
00 – Disable watchdog timer
01 – 0.5sec
10 – 1.0sec (default)
11 – 2.0sec
1 R/W IREV_EN 1
Reverse current protection (RCP) comparator control.
0 – RCP disable
1 – RCP enable (default)
0 R/W REG_RST 0
Register reset
0 – no reset (default)
1 – Reset all registers to their default values
RT9750
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Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Name Function Addr Reset
SAMPLE_EN SAMPLE_EN 0x08 0xFF
Bit Mode Name Reset Value Description
7 R/W VBUS_ADC_EN 1
Enable/disable VBUS_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
6 R/W IBUS_ADC_EN 1
Enable/disable IBUS_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
5 R/W VOUT_ADC_EN 1
Enable/disable VOUT_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
4 R/W VDROP_ADC_EN 1
Enable/disable VDROP_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
3 R/W VBAT_ADC_EN 1
Enable/disable VBAT_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
2 R/W Reserved 1 Reserved
1 R/W TBUS_ADC_EN 1
Enable/disable TBUS_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
0 R/W TBAT_ADC_EN 1
Enable/disable TBAT_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
RT9750
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Name Function Addr Reset
PROT_DLY&OCP PROT_DLY&OCP 0x09 0xA0
Bit Mode Name Reset Value Description
[7:4] R/W IOC_OCP<3:0> 1010
IOC_OCP (Input Over-Current Protection)
Offset : 0A
LSB<3:0> : 4A, 2A, 1A, 0.5A
Range Min : 0A (0b0000)
Range Max : 6.5A (0b1101)
Default : 5A (0b1010)
3 R/W LOWCHG_ALM_EN 0
Enables LOWCHG_ALM in CHG mode
0 – Disable LOWCHG_ALM (default)
1 – Enable LOWCHG_ALM
2 R/W LOWCHG_ALM 0
LOWCHG_ALM
0 – 50mA (default)
(0x15<4:0> = 00000, 0x16<7:0> = 00110010)
1 – 100mA
(0x15<4:0> = 00000, 0x16<7:0> = 01100100)
1 R/W OCP_RES 0
Controls the response of the OCP event for IBUS.
0 – Blanking mode; the device will wait 50µs before the
battery switch is disabled and latched off (default)
1 – Hiccup mode; battery switch is disabled
instantaneously, and the device will attempt to turn on
the battery switch wait 250µs to check OCP and turn
off every 100ms, up to 7 times before latching off.
0 R/W VBUS_OVP_DLY 0
Sets VBUS fault deglitch time
0 – 4s deglitch time (default)
1 – 20s deglitch time
Name Function Addr Reset
VBUS_OVP VBUS_OVP 0x0A 0x34
Bit Mode Name Reset Value Description
[6:0] R/W VBUS_OVP<6:0> 0110100
VBUS_OVP
Offset : 4.2V
LSB<6:0> : 1600mV, 800mV, 400mV, 200mV,
100mV, 50mV, 25mV
Range Min : 4.2V (0b0000000)
Range Max : 6.5V (0b1011100)
Default : 5.5V (0b0110100)

RT9750WSC

Mfr. #:
Manufacturer:
Description:
IC BATT CHARGER 6A WL-CSP-42B
Lifecycle:
New from this manufacturer.
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