DATA SHEET
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
1 ©2012 Integrated Device Technology, Inc.
Quad-Frequency Programmable
VCXO
IDT8N3QV01 Rev G
General Description
The IDT8N3QV01 is a Quad-Frequency Programmable VCXO with
very flexible frequency and pull-range programming capabilities.
The device uses IDT’s fourth generation FemtoClock® NG
technology for an optimum of high clock frequency and low phase
noise performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x
7mm x 1.55mm package.
Besides the 4 default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N3QV01 can be programmed via the I
2
C
interface to any output clock frequency between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL M and N divider registers (P, MINT, MFRAC and
N), reprogramming those registers to other frequencies under
control of FSEL0 and FSEL1 is supported. The extended
temperature range supports wireless infrastructure, tele-
communication and networking end equipment requirements. The
device is a member of the high-performance clock family from IDT.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), reprogrammable by I
2
C
I
2
C programming interface for the output clock frequency, APR
and internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
Absolute pull-range (APR) programmable from ±4.5 to
±754.5ppm
One 2.5V or 3.3V LVPECL differential clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz):
0.487ps (typical)
RMS phase jitter @ 156.25MHz (1kHz - 40MHz):
0.614ps (typical)
2.5V or 3.3V supply voltage modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
1
2
3
4
8
7
6
5
10 9
VC
OE
V
EE
VCC
nQ
Q
FSEL0
FSEL1
SCLK
SDATA
IDT8N3QV01 Rev G
10-lead Ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
Pin Assignment
Block Diagram
Q
nQ
OSC
114.285 MHz
÷MINT, MFRAC
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
I
2
C Control
Configuration Register (ROM)
(Frequency, APR, Polarity)
25
7
VC
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
A/D
7
÷P
2
IDT8N3QV01 Rev G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-VCXO
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
2 ©2012 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 VC Input
VCXO Control Voltage input. The control voltage versus frequency
characteristics are set by the ADC_GAIN[5:0] register bits.
2 OE Input Pullup
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface
levels.
3V
EE
Power Negative power supply.
5, 4 FSEL1, FSEL0 Input Pulldown
Default frequency select pins. See the Default Frequency Order Codes
section. LVCMOS/LVTTL interface levels.
6, 7
Q, nQ
Output Differential clock output. LVPECL interface levels.
8
V
CC
Power Positive power supply.
9
SDATA
Input/Output Pullup
I
2
C data input. Input: LVCMOS/LVTTL interface levels. Output: Open drain.
10
SCLK
Input Pullup
I
2
C clock input. LVCMOS/LVTTL compatible interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance
FSEL[1:0], SDATA, SCLK 5.5 pF
VC 10 pF
R
PULLUP
Input Pullup Resistor 50 k
R
PULLDOWN
Input Pulldown Resistor 50 k
IDT8N3QV01 Rev G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-VCXO
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
3 ©2012 Integrated Device Technology, Inc.
Function Tables
Table 3A. Default Frequency Selection
NOTE: The default frequency is the output frequency after power-up. One of four default frequencies is selected by FSEL[1:0]. See
programming section for details.
Table 3B. OE Configuration
NOTE: OE is an asynchronous control.
Input
OperationFSEL1 FSEL0
0 (default) 0 (default) Default frequency 0
0 1 Default frequency 1
1 0 Default frequency 2
1 1 Default frequency 3
Input
Output EnableOE
0 Outputs Q, nQ are in high-impedance state.
1 (default) Outputs are enabled.

8N3QV01EG-0081CDI8

Mfr. #:
Manufacturer:
Description:
Programmable Oscillators PROGRAMMABLE FEMTOCLOCK
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