IDT8N3QV01 Rev G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-VCXO
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
16 ©2012 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8N3QV01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8N3QV01 is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 150mA = 519.75mW
Power (outputs)
MAX
= 34.2mW/Loaded Output pair
Total Power_
MAX
(3.465V, with all outputs switching) = 519.75mW + 34.2mW = 533.95mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance
JA
for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2C/W 41°C/W
IDT8N3QV01 Rev G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-VCXO
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
17 ©2012 Integrated Device Technology, Inc.
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 4.
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
V
CC
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.8V
(V
CC_MAX
– V
OH_MAX
) = 0.8V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.5V
(V
CC_MAX
– V
OL_MAX
) = 1.5V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L
] * (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.5V)/50] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 34.2mW
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω
IDT8N3QV01 Rev G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-VCXO
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
18 ©2012 Integrated Device Technology, Inc.
Reliability Information
Table 8.
JA
vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package
Transistor Count
The transistor count for IDT8N3QV01 Rev G is: 43, 718
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2C/W 41°C/W

8N3QV01EG-0081CDI8

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Programmable Oscillators PROGRAMMABLE FEMTOCLOCK
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