IDT8N3QV01 Rev G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-VCXO
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
15 ©2012 Integrated Device Technology, Inc.
Schematic Layout
Figure 3 shows an example of IDT8N3QV01 application schematic.
In this example, the device is operated at V
CC
= 3.3V. As with any
high speed analog circuitry, the power supply pins are vulnerable to
noise. To achieve optimum jitter performance, power supply isolation
is required. The IDT8N3QV01 provides separate power supplies to
isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Figure 3. IDT8N3QV01 Application Schematic
VCC
SDATA
C2
10uF
3.3V
Set Logic
Input to
'0'
R5
133
VCC
nQ
SCLK
RU1
1K
VC
RD1
Not Install
VCC
FSEL0
To Logic
Input
pins
U1
1
2
3 6
7
8
4
5 9
10
VC
OE
VEE Q
nQ
VCC
FSEL0
FSEL1 SDATA
SCLK
BLM18BB221SN1
Ferrite Bead
1 2
R9
50
R8
82.5
Logic Control Input Examples
Set Logic
Input to
'1'
R10
50
Q
R1
SP
Optional
Y-Termination
To Logic
Input
pins
Zo = 50 Ohm
R4
133
Zo = 50 Ohm
R7
82.5
RD2
1K
3.3V
OE
VCC=3.3V
R2
SP
+
-
J1
1
2
Zo = 50 Ohm
R3
SP
Zo = 50 Ohm
C1
0.1uF
VCC
+
-
FSEL1
VCC
RU2
Not Install
C3
0.1uF
R11
50
R6
SP
