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ADF4113HVBRUZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet ADF4113HV
Rev. B | Page 3 of 20
SPECIFICATIONS
AV
DD
= DV
DD
= 3 V ± 10%, 5 V ± 10%; 13.5 V < V
P
≤ 16.5 V; AGND = DGND = CPGND = 0 V; R
SET
= 4.7 kΩ; dBm referred to 50 Ω;
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C.
Table 1.
B Version
B Chips
1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Sensitivity −15/0 −15/0 dBm min/max
0.2/3.7
0.2/3.7
GHz min/max
For lower frequencies, ensure SR > 130 V/μs
165
165
MHz max
−10/0
−10/0
dBm min/max
RF Input Frequency 0.2/3.7 0.2/3.7 GHz min/max For lower frequencies, ensure SR > 130 V/µs
0.2/4.0 0.2/4.0 GHz min/max Input level = −5 dBm
Prescaler Output Frequency 200 200 MHz max
REF
CHARACTERISTICS
REF
Input Frequency 5/150 5/150 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs
0.4/AV
DD
0.4/AV
DD
V p-p min/max
AV
DD
= 3.3 V, biased at AV
DD
/2
3
1.0/AV
DD
1.0/AV
DD
V p-p min/max
For f ≥ 10 MHz, AV
DD
= 5 V, biased at AV
DD
/2
3, 4
REF
Input Capacitance 10 10 pF max
REF
Input Current ±100 ±100 µA max
PHASE DETECTOR FREQUENCY 5 5 MHz max
I
Sink/Source R
SET
= 4.7 kΩ
High Value 640 640 μA typ
Low Value 80 80 µA typ
2.5
2.5
% typ
3.9/10
3.9/10
kΩ typ
I
Three-State Leakage Current 5 5 nA max
Sink and Source Current Matching 3 3 % typ 1 V ≤ V
CP
≤ V
P
– 1 V
I
vs. V
1.5 1.5 % typ 1 V ≤ V
CP
≤ V
P
– 1 V
2
2
% typ
V
CP
= V
P
/2
LOGIC INPUTS
0.8 × DV
DD
0.8 × DV
DD
V min
0.2 × DV
DD
0.2 × DV
DD
V max
I
/I
, Input Current ±1 ±1 µA max
C
, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
, Output High Voltage DV
DD
− 0.4 DV
DD
− 0.4 V min I
OH
= 500 µA
V
, Output Low Voltage 0.4 0.4 V max I
OL
= 500 µA
POWER SUPPLIES
AV
2.7/5.5 2.7/5.5 V min/V max
AV
DD
AV
DD
13.5/16.5
13.5/16.5
V min/V max
I
5
(AI
+ DI
) 16 11 mA max 11 mA typical
I
0.25 0.25 mA max T
A
= 25°C
Low Power Sleep Mode 1 1 µA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
−212 −212 dBc/Hz typ
1
The B chip specifications are given as typical values.
2
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3
AC coupling ensures AV
DD
/2 bias.
4
Guaranteed by characterization.
5
T
A
= 25
o
C; AV
DD
= DV
DD
= 5.5 V; P = 16; RF
IN
= 900 MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
TOT
, and subtracting 20logN (where N is the N divider
value) and 10logf
PFD
: PN
SYNTH
= PN
TOT
− 10logf
PFD
− 20logN.
ADF4113HV Data Sheet
Rev. B | Page 4 of 20
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AV
DD
= DV
DD
= 3 V ± 10%, 5 V ± 10%; 13.5 V ≤ V
P
≤ 16.5 V;
AGND = DGND = CPGND = 0 V; R
SET
= 4.7 kΩ; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Limit at T
MIN
to T
MAX
(B Version) Unit Test Conditions/Comments
t
1
20 ns min LE setup time
t
2
10 ns min DATA to CLK setup time
t
3
10 ns min DATA to CLK hold time
t
4
25 ns min CLK high duration
t
5
25 ns min CLK low duration
t
6
10 ns min CLK to LE setup time
t
7
20 ns min LE pulse width
Timing Diagram
CLK
DATA
LE
LE
DB23 (MSB) DB22 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
06223-002
Figure 2. Timing Diagram
Data Sheet ADF4113HV
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AV
DD
to GND
1
−0.3 V to +7 V
AV
DD
to DV
DD
−0.3 V to +0.3 V
V
P
to GND −0.3 V to +18 V
Digital I/O Voltage to GND −0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND −0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B to GND −0.3 V to V
DD
+ 0.3 V
RF
IN
A to RF
IN
B
±320 mV
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Reflow, Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
1
GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
The transistor count is 12,150 (CMOS) and 348 (bipolar).
THERMAL RESISTANCE
Table 4. Thermal Resistance
Package Type θ
JA
Unit
TSSOP 150.4 °C/W
LFCSP (Paddle Soldered)
1
62.82 °C/W
1
Two signal planes (that is, on top and bottom surfaces), two buried planes,
and four thermal vias.
ESD CAUTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADF4113HVBRUZ-RL7

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Buy ADF4113HVBRUZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL High VTG Charge Pump
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