ADF4113HV Data Sheet
Rev. B | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
CP
PGND
AGND
AV
DD
R
FIN
A
R
FIN
B
R
SET
REF
IN
16
15
14
13
12
11
10
9
DV
DD
MUXOUT
LE
CE
DGND
CLK
DATA
V
P
ADF4113HV
TOP VIEW
(Not to Scale)
6223-003
Figure 3. TSSOP Pin Configuration
06223-004
AGND
AGND
RF
IN
B
RF
IN
A
DATA
LE
MUXOUT
CLK
CE
AV
DD
AV
DD
REF
IN
DGND
DGND
V
P
R
SET
CP
DV
DD
DV
DD
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
14
13
12
1
3
4
15
11
CPGND
2
5
7
6
8
9
10
19
20
18
17
16
ADF4113HV
TOP VIEW
(Not to Scale)
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No. Mnemonic Description
1 19 R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
SET
pin is 0.56 V for the ADF4113HV. The relationship between
I
CP
and R
SET
is I
CPmax
= 3/R
SET
. Therefore, with R
SET
= 4.7 kΩ, I
CPmax
= 640 A.
2 20 CP
Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter; in turn, this
drives the external VCO.
3 1 CPGND Charge Pump Ground. CPGND is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RF
IN
B
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF.
6 5 RF
IN
A Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
7 6, 7 AV
DD
Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
DD
must be the same value
as DV
DD
.
8 8 REF
IN
Reference Input. This pin is a CMOS input with a nominal threshold of V
DD
/2, and an equivalent
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be
ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE
Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device depending on the status of the
Power-Down Bit PD1.
11 12 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
14 15 MUXOUT
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the
scaled reference frequency to be externally accessed.
15 16, 17 DV
DD
Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane (1µF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 µF
capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical
but should still be within 5 mm of the pin. DV
DD
must have the same value as AV
DD
.
16 18 V
P
Charge Pump Power Supply. V
P
can range from 13.5 V to 16.5 V and should be decoupled
appropriately.
N/A 21 EPAD Exposed Pad. The exposed pad must be connected to AGND.
