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AD7866ARUZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
REV. A–12–
AD7866
Analog Input Ranges
The analog input range for the AD7866 can be selected to be 0 V
to V
REF
or 2 V
REF
with either straight binary or twos complement
output coding. The RANGE pin is used to select both the analog
input range and the output coding, as shown in Figures 5 to 8.
On the falling edge of CS, point A, the logic level of the RANGE
pin is checked to determine the analog input range of the next
conversion. If this pin is tied to a logic low, the analog input
range will be 0 V to V
REF
and the output coding from the part will
be straight binary (for the next conversion). If this pin is at a logic
high when CS goes low, the analog input range will be 2 V
REF
and
the output coding for the part will be twos complement. How-
ever, if after the falling edge of CS, the logic level of the
RANGE pin has changed upon the eighth falling SCLK edge,
point B, the output coding will change to the other option without
any change in the analog input range. So for the next conversion,
twos complement output coding could be selected with a 0 V to
V
REF
input range, for example, if the RANGE pin is low upon
the falling edge of CS and high upon the eighth falling SCLK
edge, as shown in Figure 7. Figures 5 to 8 show examples of
timing diagrams for selections of different analog input ranges
with various output coding formats. Table I summarizes the
required logic level of the RANGE pin for each selection. Note
that the analog input range selected must not exceed V
DD
. The
logic input A0 is used to select the pair of channels to be converted
simultaneously. The logic state of this pin is also checked upon
the falling edge of CS, and the multiplexers are set up for the
next conversion. If it is low, the following conversion will be
performed on Channel 1 of each ADC; if it is high, the following
conversion will be performed on Channel 2 of each ADC.
Handling Bipolar Input Signals
Figure 9 shows how useful the combination of the 2 V
REF
input range and the twos complement output coding scheme is
for handling bipolar input signals. If the bipolar input signal
is biased about V
REF
and twos complement output coding is
selected, then V
REF
becomes the zero code point, –V
REF
is
negative full-scale, and +V
REF
becomes positive full-scale with a
dynamic range of 2 V
REF
.
Transfer Functions
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is V
REF
/4096.
The ideal transfer characteristic for the AD7866 when straight
binary coding is selected is shown in Figure 10, and the ideal
transfer characteristic for the AD7866 when twos complement
coding is selected is shown in Figure 11.
Table I. Analog Input and Output Coding Selection
Range Level Range Level
@ Point A
1
@ Point B
2
Input Range
3
Output Coding
3
Low Low 0 V to V
REF
Straight Binary
High High V
REF
± V
REF
Twos Complement
Low High V
REF
/2 ± V
REF
/2 Twos Complement
High Low 0 V to 2 V
REF
Straight Binary
NOTES
1
Point A = Falling edge of CS.
2
Point B = Eighth falling edge of SCLK.
3
Selected for next conversion.
STRAIGHT BINARY
0V TO V
REF
INPUT RANGE
CS
SCLK
RANGE
D
OUT
A
D
OUT
B
1816 161
AB
Figure 5. Selecting 0 V to V
REF
Input Range with Straight Binary Output Coding
CS
SCLK
RANGE
D
OUT
A
D
OUT
B
1816 161
AB
V
REF
ⴞ V
REF
INPUT RANGE
TWOS COMPLEMENT
Figure 6. Selecting V
REF
±
V
REF
Input Range with Twos Complement Output Coding
REV. A
AD7866
–13–
CS
SCLK
RANGE
D
OUT
A
D
OUT
B
1816 161
AB
V
REF
/2 ⴞ V
REF
/2
INPUT RANGE
TWOS COMPLEMENT
Figure 7. Selecting V
REF
/2
±
V
REF
/2 Input Range with Twos Complement Output Coding
CS
SCLK
RANGE
D
OUT
A
D
OUT
B
1816 161
AB
0V TO 2 ⴛ V
REF
INPUT RANGE
STRAIGHT BINARY
Figure 8. Selecting 0 V to 2
V
REF
Input Range with Straight Binary Output Coding
REF SELECT
V
REF
AD7866
D
OUT
D
CAP
A
D
CAP
B
V
DRIVE
V
IN
470nF
470nF
100nF
V
REF
R4
R3
R2
V
R1
V
0V
TWOS
COMPLEMENT
011
111
+V
REF
V
REF
–V
REF
(= 2 ⴛ V
REF
)
000
000
100
000
(= 0V)
R1 = R2 = R3 = R4
V
DD
V
DD
DSP/␮P
Figure 9. Handling Bipolar Signals with the AD7866
000...000
0V
ANALOG INPUT
111...111
000...001
000...010
111...110
111...000
011...111
1LSB
V
REF
– 1LSB
1LSB = V
REF
/4096
ADC CODE
Figure 10. Straight Binary Transfer
Characteristic with 0 V to V
REF
Input Range
100...000
ANALOG INPUT
011...110
100...001
100...010
000...001
111...111
1LSB = 2 ⴛ V
REF
/4096
ADC CODE
011...111
000...000
+V
REF
– 1LSB–V
REF
+ 1LSB
V
REF
– 1LSB
Figure 11. Twos Complement Transfer
Characteristic with V
REF
±
V
REF
Input Range
REV. A–14–
AD7866
Digital Inputs
The digital inputs applied to the AD7866 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digital
inputs applied can go to 7 V and are not restricted by the V
DD
+
0.3 V limit as on the analog inputs. See maximum ratings.
Another advantage of SCLK, RANGE, REF SELECT, A0, and
CS not being restricted by the V
DD
+ 0.3 V limit is that power
supply sequencing issues are avoided. If one of these digital inputs
is applied before V
DD
, there is no risk of latch-up, as there
would be on the analog inputs if a signal greater than 0.3 V were
applied prior to V
DD
.
V
DRIVE
The AD7866 also has the V
DRIVE
feature, which controls the
voltage at which the serial interface operates. V
DRIVE
allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7866 was operated with a V
DD
of 5 V, the
V
DRIVE
pin could be powered from a 3 V supply, allowing a large
dynamic range with low voltage digital processors. For example,
the AD7866 could be used with the 2 V
REF
input range, with a
V
DD
of 5 V while still being able to interface to 3 V digital parts.
REFERENCE CONFIGURATION OPTIONS
The AD7866 has various reference configuration options. The
REF SELECT pin allows the choice of using an internal 2.5 V
reference or applying an external reference, or even an individual
external reference for each on-chip ADC if desired. If the REF
SELECT pin is tied to AGND, then the on-chip 2.5 V reference
is used as the reference source for both ADC A and ADC B. In
addition, pins V
REF
, D
CAP
A, and D
CAP
B must be tied to decoupling
capacitors (100 nF, 470 nF, and 470 nF recommended,
respectively). If the REF SELECT pin is tied to a logic high, an
external reference can be supplied to the AD7866 through the
V
REF
pin to overdrive the on-chip reference, in which case
decoupling capacitors are required on D
CAP
A and D
CAP
B again.
However, if the V
REF
pin is tied to AGND while REF SELECT
is tied to a logic low, an individual external reference can be
applied to both ADC A and ADC B through pins D
CAP
A and
D
CAP
B, respectively. Table II summarizes these reference options.
For specified performance, the last configuration was used with
the same reference voltage applied to both D
CAP
A and D
CAP
B.
The connections for the relevant reference pins are shown in the
typical connection diagrams. If the internal reference is being
used, the V
REF
pin should have a 100 nF capacitor connected to
AGND very close to the V
REF
pin. These connections are shown
in Figure 12.
D
CAP
B
D
CAP
A
V
REF
470nF
AD7866
470nF
100nF
Figure 12. Relevant Connections when Using an
Internal Reference
D
CAP
B
D
CAP
A
V
REF
AD7866
V
REF
REF SELECT
Figure 13. Relevant Connections when Applying
an External Reference at D
CAP
A and/or D
CAP
B
Figure 14. Relevant Connections when Applying
an External Reference at V
REF
Figure 13 shows the connections required when an external
reference is applied to D
CAP
A and D
CAP
B. In this example, the
same reference voltage is applied at each pin; however, a different
voltage may be applied at each of these pins for each on-chip
ADC. An external reference applied at these pins may have a
range from 2 V to 3 V, but for specified performance it must be
within ± 1% of 2.5 V. Figure 14 shows the third option, which is
to overdrive the internal reference through the V
REF
pin. This is
possible due to the series resistance from the V
REF
pin to the
internal reference. This external reference can have a range from
2 V to 3 V; but again, to get as close as possible to the specified
performance, a 2.5 V reference is desirable. D
CAP
A and D
CAP
B
decouple each on-chip reference buffer, as shown in Figure 15.
Table II. Reference Selection
Reference Option REF SELECT V
REF
1
D
CAP
A and D
CAP
B
2
Internal Low Decoupling Capacitor Decoupling Capacitor
Externally through V
REF
High External Reference Decoupling Capacitor
Externally through
D
CAP
A and/or D
CAP
B Low AGND External Reference A and/or
Reference B
NOTES
1
Recommended value of decoupling capacitor = 100 nF.
2
Recommended value of decoupling capacitor = 470 nF.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7866ARUZ-REEL

Mfr. #:
Buy AD7866ARUZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Dual 1MSPS 12-Bit 2-Ch SAR
Lifecycle:
New from this manufacturer.
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