REV. A–16–
AD7866
terminated, and D
OUT
A and D
OUT
B will go back into three-
state. If CS is brought high before the second SCLK falling
edge, the part will remain in normal mode and will not power
down. This will avoid accidental power-down due to glitches on
the CS line.
To exit this mode of operation and power up the AD7866 again,
a dummy conversion is performed. On the falling edge of CS,
the device will begin to power up, and will continue to power up
as long as CS is held low until after the falling edge of the tenth
SCLK. In the case of an external reference, the device will be
fully powered up once 16 SCLKs have elapsed, and valid data
will result from the next conversion, as shown in Figure 18. If
CS is brought high before the second falling edge of SCLK, the
AD7866 will again go into partial power-down. This avoids
accidental power-up due to glitches on the CS line; although the
device may begin to power up on the falling edge of CS, it will
power down again on the rising edge of CS. If the AD7866 is
already in partial power-down mode and CS is brought high
between the second and tenth falling edges of SCLK, the device
will enter full power-down mode. For more information on the
power-up times associated with partial power-down in various
configurations, see the Power-Up Times section.
Full Power-Down Mode
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are required,
as power-up from a full power-down takes substantially longer
than that from partial power-down. This mode is more suited to
applications where a series of conversions performed at a rela-
tively high throughput rate would be followed by a long period
of inactivity and thus power-down. When the AD7866 is in full
power-down, all analog circuitry is powered down. Full power-
down is entered in a similar way as partial power-down, except
the timing sequence shown in Figure 17 must be executed twice.
The conversion process must be interrupted in a similar fashion
by bringing CS high anywhere after the second falling edge of
SCLK and before the tenth falling edge of SCLK. The device
will enter partial power-down at this point. To reach full
power-down, the next conversion cycle must be interrupted in
the same way, as shown in Figure 19. Once CS has been
brought high in this window of SCLKs, the part will power
down completely.
Note that it is not necessary to complete the 16 SCLKs once
CS has been brought high to enter a power-down mode.
To exit full power-down and power the AD7866 up again, a
dummy conversion is performed, as when powering up from
partial power-down. On the falling edge of CS, the device will
begin to power up and will continue to power up as long as CS
is held low until after the falling edge of the tenth SCLK. The
power-up time required must elapse before a conversion can be
initiated, as shown in Figure 20. See the Power-Up Times sec-
tion for the power-up times associated with the AD7866.
POWER-UP TIMES
The AD7866 has two power-down modes, partial power-down
and full power-down, which are described in detail in the Modes
of Operation section. This section deals with the power-up time
required when coming out of either of these modes. It should be
noted that the power-up times quoted apply with the recommended
capacitors on the V
REF
, D
CAP
A, and D
CAP
B pins in place.
To power up from full power-down, approximately 4 ms should
be allowed from the falling edge of CS, shown in Figure 20 as
t
POWER UP
. Powering up from partial power-down requires much
less time. If the internal reference is being used, the power-up
time is typically 4 µs; but if an external reference is being used,
the power-up time is typically 1 µs. This means that with any
frequency of SCLK up to 20 MHz, one dummy cycle will always
be sufficient to allow the device to power up from partial power-
down when using an external reference (see Figure 18). Once
the dummy cycle is complete, the ADC will be fully powered up
and the input signal will be acquired properly. A dummy cycle
may well be sufficient to power up the part when using an internal
reference also, provided the SCLK is slow enough to allow the
required power-up time to elapse before a valid conversion is
requested. In addition, it should be ensured that the quiet time,
t
QUIET
, has still been allowed from the point where the bus goes
back into three-state after the dummy conversion to the next
falling edge of CS. Alternatively, instead of slowing the SCLK to
make the dummy cycle long enough, the CS high time could
just be extended to include the required power-up time (as in
Figure 20) when powering up from full power-down.
Different power-up time is needed when coming out of partial
power-down for two cases where an internal or external refer-
ence is being used, primarily because of the on-chip reference
buffers. They power down in partial power-down mode and must
be powered up again if the internal reference is being used,
but they do not need to be powered up again if an external
reference is being used. The time needed to power up these
buffers is not just their own power-up time but also the time
required to charge up the decoupling capacitors present on pins
V
REF
, D
CAP
A, and D
CAP
B.
It should also be noted that during power-up from partial
power-down, the track-and-hold, which was in hold mode while
the part was powered down, returns to track mode after the first
SCLK edge the part receives after the falling edge of CS. This is
shown as point A in Figure 18.
When power supplies are first applied to the AD7866, the ADC
may power up in either of the power-down modes or the normal
mode. Because of this, it is best to allow a dummy cycle to elapse
to ensure that the part is fully powered up before attempting a
valid conversion. Likewise, if the part is to be kept in the partial
power-down mode immediately after the supplies are applied,
two dummy cycles must be initiated. The first dummy cycle must
hold CS low until after the tenth SCLK falling edge (see Figure 16);
in the second cycle, CS must be brought high before the tenth
SCLK edge but after the second SCLK falling edge (see Figure 17).
Alternatively, if the part is to be placed in full power-down
mode when the supplies have been applied, three dummy cycles
must be initiated. The first dummy cycle must hold CS low
until after the tenth SCLK falling edge (see Figure 16); the sec-
ond and third dummy cycles place the part in full power-down
(see Figure 19). See also the Modes of Operation section.
Once supplies are applied to the AD7866, enough time must be
allowed for any external reference to power up and charge any
reference capacitor to its final value, or enough time must be
allowed for the internal reference buffer to charge the various
reference buffer decoupling capacitors to their final values.
