REV. A–6–
AD7866
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD7866
REF SELECT
A0
D
CAP
B
AGND
V
B2
V
B1
V
A2
V
A1
AGND
D
CAP
A
V
REF
CS
SCLK
V
DRIVE
D
OUT
B
D
OUT
A
DGND
DV
DD
AV
DD
RANGE
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to GND, the on-chip 2.5 V reference
is used as the reference source for both ADC A and ADC B. In addition, pins V
REF
, D
CAP
A, and D
CAP
B
must be tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external refer-
ence can be supplied to the AD7866 through the V
REF
pin, in which case decoupling capacitors are
required on D
CAP
A and D
CAP
B. However, if the V
REF
pin is tied to AGND while REF SELECT is tied to
a logic low, an individual external reference can be applied to both ADC A and ADC B through pins
D
CAP
A and D
CAP
B, respectively. See the Reference Configuration Options section.
2, 9 D
CAP
B, D
CAP
A Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective
ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a system.
Depending on the polarity of the REF SELECT pin and the configuration of the V
REF
pin, these
pins can also be used to input a separate external reference to each ADC. The range of the external
reference is dependent on the analog input range selected. See the Reference Configuration
Options section.
3, 8 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7866. All analog input signals
and any external reference signal should be referred to this AGND voltage. Both of these pins should
connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the
same potential and must not be more than 0.3 V apart, even on a transient basis.
4, 5 V
B2
,
V
B1
Analog Inputs of ADC B. Single-ended analog input channels. The input range on each channel is 0 V
to V
REF
or a 2 V
REF
range depending on the polarity of the RANGE pin upon the falling edge of CS.
6, 7 V
A2
,
V
A1
Analog Inputs of ADC A. Single-ended analog input channels. The input range on each channel is 0 V
to V
REF
or a 2 V
REF
range depending on the polarity of the RANGE pin upon the falling edge of CS.
10 V
REF
Reference Decoupling and External Reference Selection. This pin is connected to the internal reference
and requires a decoupling capacitor. The nominal reference voltage is 2.5 V, which appears at the pin;
however, if the internal reference is to be used externally in a system, it must be taken from either the
D
CAP
A or D
CAP
B pins. This pin is also used in conjunction with the REF SELECT pin when
applying an external ref
erence to the AD7866. See the REF SELECT pin description.
REV. A
AD7866
–7–
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Mnemonic Function
11 RANGE Analog Input Range and Output Coding Selection. Logic input. The polarity on this pin will
determine what input range the analog input channels on the AD7866 will have, and will also select
the type of output coding the ADC will use for the conversion result. On the falling edge of CS, the
polarity of this pin is checked to determine the analog input range of the next conversion. If this pin
is tied to a logic low, the analog input range is 0 V to V
REF
and the output coding from the part will
be straight binary (for the next conversion). If this pin is tied to a logic high when CS goes low, the
analog input range is 2 V
REF
and the output coding for the part will be twos complement. How-
ever, if after the falling edge of CS the logic level of the RANGE pin has changed upon the eighth
SCLK falling edge, the output coding will change to the other option without any change in the
analog input range. (See the Analog Input and ADC Transfer Function sections.)
12 AV
DD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the
AD7866. The AV
DD
and DV
DD
voltages ideally should be at the same potential and must not be
more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND.
13 DV
DD
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7866. The DV
DD
and AV
DD
voltages should ideally be at the same potential and must not be
more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
14 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The
DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V
apart even on a transient basis.
15, 16 D
OUT
A, D
OUT
B Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously
from the simultaneous conversions of both ADCs. The data stream consists of one leading zero
followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided
MSB first. If CS is held low for another 16 SCLK cycles after the conversion data has been output
on either D
OUT
A or D
OUT
B, the data from the other ADC follows on the D
OUT
pin. This allows data
from a simultaneous conversion on both ADCs to be gathered in serial format on either D
OUT
A or
D
OUT
B alone using only one serial port. See the Serial Interface section.
17 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
will operate. This pin should be decoupled to DGND.
18 SCLK Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the
AD7866. This clock is also used as the clock source for the conversion process.
19 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7866 and frames the serial data transfer.
20 A0 Multiplexer Select. Logic input. This input is used to select the pair of channels to be converted
simultaneously, i.e., Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B.
The logic state of this pin is checked upon the falling edge of CS, and the multiplexer is set up for
the next conversion. If it is low, the following conversion will be performed on Channel 1 of each ADC;
if it is high, the following conversion will be performed on Channel 2 of each ADC.
REV. A–8–
AD7866
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB above
the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This applies to Straight Binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in Offset Error between the two channels.
Gain Error
This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from
the ideal (i.e., V
REF
– 1 LSB) after the offset error has been
adjusted out.
Gain Error Match
This is the difference in Gain Error between the two channels.
Zero Code Error
This applies when using the twos complement output coding
option, in particular with the 2 V
REF
input range as –V
REF
to
+V
REF
biased about the V
REF
point. It is the deviation of the
midscale transition (all 1s to all 0s) from the ideal V
IN
voltage,
i.e., V
REF
– 1 LSB.
Zero Code Error Match
This refers to the difference in Zero Code Error between the
two channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular with the 2 V
REF
input range as –V
REF
to
+V
REF
biased about the V
REF
point. It is the deviation of the last
code transition (011 . . . 110) to (011 . . . 111) from the ideal
(i.e., +V
REF
– 1 LSB) after the Zero Code Error has been
adjusted out.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular with the 2 V
REF
input range as –V
REF
to
+V
REF
biased about the V
REF
point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal
(i.e., –V
REF
+ 1 LSB) after the Zero Code Error has been
adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal-to-(Noise + Distortion) Ratio (SNDR)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (f
S
/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of har-
monics to the fundamental. For the AD7866, it is defined as:
THD db
VVVVV
V
()
=
++++
20
2
2
3
2
4
2
5
2
6
2
1
log
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum. But for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa ± nfb where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those for
which neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
The AD7866 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dB.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale
(2 V
REF
), 455 kHz sine wave signal to all unselected input
channels and determining how much that signal is attenuated in the
selected channel with a 10 kHz signal (0 V to V
REF
). The figure
given is the worst-case across all four channels for the AD7866.
PSR (Power Supply Rejection)
See the Performance Curves section.

AD7866ARUZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Dual 1MSPS 12-Bit 2-Ch SAR
Lifecycle:
New from this manufacturer.
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