MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
16 ______________________________________________________________________________________
tantalum or electrolytic capacitors. Ferrite beads with
additional decoupling capacitors forming a pi-network
could also improve performance.
The analog and digital power-supply inputs AV
DD3.3
,
AV
CLK
, and DV
DD3.3
allow a +3.135V to +3.465V sup-
ply voltage range. The analog and digital power-supply
inputs AV
DD1.8
and DV
DD1.8
allow a +1.71V to +1.89V
supply voltage range.
The MAX5876 is packaged in a 68-pin QFN-EP pack-
age, providing greater design flexibility, and optimized
DAC AC performance. The EP enables the use of nec-
essary grounding techniques to ensure highest perfor-
mance operation. Thermal efficiency is not the key
factor, since the MAX5876 features low-power opera-
tion. The exposed pad ensures a minimum inductance
ground connection between the DAC and the PCB’s
ground layer.
The data converter die attaches to an EP lead frame with
the back of this frame exposed at the package bottom
surface, facing the PCB side of the package. This allows
for a solid attachment of the package to the PCB with
standard infrared reflow (IR) soldering techniques. A spe-
cially created land pattern on the PCB, matching the size
of the EP (6mm x 6mm), ensures the proper attachment
and grounding of the DAC (refer to the MAX5878 EV kit).
Designing vias into the land area and implementing large
ground planes in the PCB design allow for the highest
performance operation of the DAC. Use an array of at
least 4 x 4 vias ( 0.3mm diameter per via hole and
1.2mm pitch between via holes) for this 68-pin QFN-EP
package. Connect the MAX5876 exposed paddle to
GND. Vias connect the land pattern to internal or external
copper planes to spread heat. Use as many vias as pos-
sible to the ground plane to minimize inductance.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every indi-
vidual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees a
monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
MAX5876
12
OUTIP/OUTQP
OUTIN/OUTQN
DATA11–DATA0
GND
25
50
25
OUTP
OUTN
Figure 8. Differential Output Configuration
MAX5876
12
OUTIP/OUTQP
OUTIN/OUTQN
DATA11–DATA0
0.1µF
AV
DD1.8
DV
DD1.8
0.1µF
0.1µF 0.1µF
AV
DD3.3
DV
DD3.3
0.1µF
AV
CLK
BYPASSING—DAC LEVEL
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
Figure 9. Recommended Power-Supply Decoupling and
Bypassing Circuitry
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 17
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum can
be derived from the DAC’s resolution (N bits):
SNR
dB
= 6.02
dB
x N + 1.76
dB
However, noise sources such as thermal noise, reference
noise, clock jitter, etc., affect the ideal reading; therefore,
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first four harmonics, and the
DC offset.
Noise Spectral Density
The DAC output noise floor is the sum of the quantiza-
tion noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal components) to the RMS
value of their next-largest distortion component. SFDR
is usually measured in dBc and with respect to the car-
rier frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or to
Nyquist.
Two-/Four-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dBFS)
of the worst 3rd-order (or higher) IMD product(s) to either
output tone.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with wideband code-
division multiple-access (W-CDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch
impulse is found by integrating the voltage of the glitch
at the midscale transition over time. The glitch impulse
is usually specified in pVs.
MAX5878
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
18 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
68L QFN.EPS
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM

MAX5876EGK+TD

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 2Ch 250Msps DAC
Lifecycle:
New from this manufacturer.
Delivery:
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