PIN NAME FUNCTION
1 B0N Complementary Data Bit 0 (LSB)
2–9 N.C. No Connection. Leave floating or connect to GND.
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36
GND Ground
11 DV
DD3.3
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
14, 21, 22, 31,
32
AV
DD3.3
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1µF capacitor to GND.
16 REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF
capacitor to GND. REFIO can be driven with an external reference source. See Table 1.
17 FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2kΩ resistor between FSADJ and DACREF. See Table 1.
18 DACREF
Current-Set Resistor Return Path. Internally connected to GND. Do not use as an external
ground connection.
19, 34 AV
DD1.8
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1µF capacitor to GND.
24 OUTQN Complementary Q-DAC Output. Negative terminal for current output.
25 OUTQP Q-DAC Output. Positive terminal for current output.
28 OUTIN Complementary I-DAC Output. Negative terminal for current output.
29 OUTIP I-DAC Output. Positive terminal for current output.
35 AV
CLK
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
37 CLKN
Complementary Converter Clock Input. Negative input terminal for LVDS/LVPECL-compatible
differential converter clock. Internally biased to AV
CLK
/ 2.
38 CLKP
Converter Clock Input. Positive input terminal for LVDS/LVPECL-compatible differential converter
clock. Internally biased to AV
CLK
/ 2.
39 TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-
complement input format. Set TORB to a CMOS-logic-low level to indicate an offset binary input
format. TORB has an internal pulldown resistor.
40 PD
Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode.
Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor.
41 XORN
Complementary LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow
the data stream to pass unchanged to the DAC input. Set XORN low and XORP high to invert the
DAC input data. If unused, connect XORN to DV
DD1.8
.
42 XORP
LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow the data stream to
pass unchanged to the DAC input. Set XORN low and XORP high to invert the DAC input data. If
unused, connect XORP to GND.
