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MAX5876EGK+TD

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input Compliance
Range
V
REFIOCR
0.125 1.260
V
Reference Input Resistance
R
REFIO
10 kΩ
Reference Voltage Drift
TCO
REF
±25
ppm/°C
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time t
FALL
90% to 10% (Note 5) 0.7 ns
Output Rise Time t
RISE
10% to 90% (Note 5) 0.7 ns
Output-Voltage Settling Time
t
SETTLE
Output settles to 0.025% FS (Note 5) 14 ns
Output Propagation Delay t
PD
Excluding data latency (Note 5) 1.1 ns
Glitch Impulse Measured differentially 1
pV•s
I
OUTFS
= 2mA 30
Output Noise n
OUT
I
OUTFS
= 20mA 30
pA/√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
t
SETUP
Referenced to rising edge of clock (Note 6)
-1.2
ns
Data to Clock Hold Time
t
HOLD
Referenced to rising edge of clock (Note 6) 2.0 ns
Latency to I output 9
Data Latency
Latency to Q output 8
Clock
Cycles
Minimum Clock Pulse-Width High
t
CH
CLKP, CLKN 0.9 ns
Minimum Clock Pulse-Width Low
t
CL
CLKP, CLKN 0.9 ns
LVDS LOGIC INPUTS (B11P/B11N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)
Differential Input-Logic High V
IH
100
mV
Differential Input-Logic Low V
IL
-100
mV
Common-Mode Voltage Range V
CMR
1.125 1.375
V
Differential Input Resistance R
IN
(Note 7)
110
Ω
Input Capacitance C
IN
2.5 pF
CMOS LOGIC INPUTS (PD, TORB)
Input-Logic High V
IH
0.7 x
DV
DD3.3
V
Input-Logic Low V
IL
0.3 x
DV
DD3.3
V
Input Leakage Current I
IN
-20 1
+20
µA
PD, TORB Internal Pulldown
Resistance
V
PD
= V
TORB
= 3.3V 1.5 MΩ
Input Capacitance C
IN
2.5 pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
> 1.5
Differential Input
Voltage Swing
Square wave
> 0.5
V
P-P
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
Note 2: Specifications at T
A
≥ +25°C are guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design.
Note 3: Nominal full-scale current I
OUTFS
= 32 x I
REF
.
Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5876.
Note 5: Parameter measured single-ended into a 50Ω termination resistor.
Note 6: Not production tested. Guaranteed by design.
Note 7: No termination resistance between XORP and XORN.
Note 8: A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance.
Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Differential Input Slew Rate
SR
CLK
(Note 8)
>100
V/µs
External Common-Mode Voltage
Range
V
COM
AV
CLK
/ 2
±0.3
V
Input Resistance R
CLK
5kΩ
Input Capacitance C
CLK
2.5 pF
POWER SUPPLIES
AV
DD3.3
3.135
3.3
3.465
Analog Supply Voltage Range
AV
DD1.8
1.710
1.8
1.890
V
DV
DD3.3
3.135
3.3
3.465
Digital Supply Voltage Range
DV
DD1.8
1.710
1.8
1.890
V
Clock Supply Voltage Range
AV
CLK
3.135
3.3
3.465
V
f
DAC
= 250Msps, f
OUT
= 16MHz 52 58 mA
I
AVDD3.3 +
I
AVCLK
Power-down 1 µA
f
DAC
= 250Msps, f
OUT
= 16MHz 31 36 mA
Analog Supply Current
I
AVDD1.8
Power-down 1 µA
f
DAC
= 250Msps, f
OUT
= 16MHz
0.15
1mA
I
DVDD3.3
Power-down 1 µA
f
DAC
= 250Msps, f
OUT
= 16MHz 33 40 mA
Digital Supply Current
I
DVDD1.8
Power-down 4 µA
f
DAC
= 250Msps, f
OUT
= 16MHz
287 331
mW
Power Dissipation P
DISS
Power-down 16 µW
Power-Supply Rejection Ratio PSRR
AV
DD3.3
= AV
CLK
= DV
DD3.3
= +3.3V ±5%
(Notes 8, 9)
-0.1 +0.1
%FS/V
MAX5876
12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
6 _______________________________________________________________________________________
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
DAC
= 50Msps)
MAX5876 toc01
f
OUT
(MHz)
SFDR (dBc)
2015105
20
40
60
80
100
0
025
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
DAC
= 100Msps)
MAX5876 toc02
f
OUT
(MHz)
SFDR (dBc)
40302010
20
40
60
80
100
0
050
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
DAC
= 150Msps)
MAX5876 toc03
f
OUT
(MHz)
SFDR (dBc)
60453015
20
40
60
80
100
0
075
0dBFS
-6dBFS
-12dBFS
Typical Operating Characteristics
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference, V
REFIO
= +1.25V, R
L
= 50Ω double-terminated,
I
OUTFS
= 20mA, T
A
= +25°C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
DAC
= 200Msps)
MAX5876 toc04
f
OUT
(MHz)
SFDR (dBc)
80604020
20
40
60
80
100
0
0 100
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
DAC
= 250Msps)
MAX5876 toc05
f
OUT
(MHz)
SFDR (dBc)
100755025
20
40
60
80
100
0
0125
-12dBFS
-6dBFS
0dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
DAC
= 100Msps)
MAX5876 toc06
f
OUT
(MHz)
TWO-TONE IMD (dBc)
353025201510
-90
-80
-75
-70
-100
540
-12dBFS
-95
-85
-6dBFS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MAX5876EGK+TD

Mfr. #:
Buy MAX5876EGK+TD
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 2Ch 250Msps DAC
Lifecycle:
New from this manufacturer.
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