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MC10EP446FAG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 11
1 Publication Order Number:
MC10EP446/D
MC10EP446, MC100EP446
3.3 V/5 V 8‐Bit
CMOS/ECL/TTL Data Input
Parallel/Serial Converter
Description
The MC10/100EP446 is an integrated 8−bit parallel to serial data
converter. The device is designed with unique circuit topology to
operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence
from parallel data into a serial data stream is from bit D0 to D7. The
parallel input pins D0−D7 are configurable to be threshold controlled by
CMOS, ECL, or TTL level signals. The serial data rate output can be
selected at internal clock data rate or twice the internal clock data rate
using the CKSEL pin.
Control pins are provided to reset (SYNC) and disable internal clock
circuitry (CKEN). In either CKSEL modes, the internal flip−flops are
triggered on the rising edge for CLK and the multiplexers are switched
on the falling edge of CLK, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
Additionally, V
BB
pin is provided for single−ended input condition.
The 100 Series devices contain temperature compensation network.
Features
• 3.2 Gb/s Typical Data Rate Capability
• Differential Clock and Serial Outputs
• V
BB
Output for Single-ended Input Applications
• Asynchronous Data Reset (SYNC)
• PECL Mode Operating Range:
V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
• NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Parallel Interface Can Support PECL, TTL or CMOS
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
LQFP−32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
*For additional marking information, refer to
Application Note AND8002/D.
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb−Free Package
MCxxx
EP446
AWLYYWWG
QFN32
MN SUFFIX
CASE 488AM
32
1
MCxxx
EP446
AWLYYWWG
G
1
(Note: Microdot may be in either location)
MC10EP446, MC100EP446
http://onsemi.com
2
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
Figure 1. LQFP−32 Pinout (Top View)
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
D0
D1
D3
D4
D7
V
CC
S
OUT
V
EE
V
BB2
V
CC
CKSEL
V
EF
V
EE
PCLK
PCLK
D2
D5
D6
S
OUT
V
CF
SYNC
SYNC
V
CC
CLK
CLK
V
BB1
CKEN
CKEN
V
EE
V
CC
V
CC
V
CC
MC10EP446
MC100EP446
Figure 2. QFN−32 Pinout (Top View)
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
12345678
24 23 22 21 20 19 18 17
Exposed Pad (EP)
D0
D1
D3
D4
D7
V
CC
CKSEL
D2
D5
D6
CLK
CLK
V
BB1
CKEN
CKEN
V
EE
S
OUT
V
EE
PCLK
PCLK
S
OUT
V
CC
V
CC
V
CC
V
CC
V
EE
V
BB2
V
EF
V
CF
SYNC
SYNC
V
CC
Table 1. PIN DESCRIPTION
PIN FUNCTION
D0*−D7* ECL, CMOS, or TTL Parallel Data Input
S
OUT
, S
OUT
ECL Differential Serial Data Output
CLK*, CLK* ECL Differential Clock Input
PCLK, PCLK ECL Differential Parallel Clock Output
SYNC*, SYNC** ECL Conversion Synchronizing Differential Input (Reset)***
CKSEL* ECL Clock Input Selector
CKEN*, CKEN* ECL Clock Enable Differential Input
V
CF
ECL, CMOS, or TTL Input Selector
V
EF
ECL Reference Mode Connection
V
BB1
, V
BB2
Reference Voltage Output
V
CC
Positive Supply
V
EE
Negative Supply
* Pins will default LOW when left open.
**Pins will default HIGH when left open.
***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK
initiates the conversion process synchronously on the next rising edge of CLK.
MC10EP446, MC100EP446
http://onsemi.com
3
Table 2. TRUTH TABLE
Pin
Function
HIGH LOW
CKSEL
S
OUT
: PCLK = 8:1
CLK: S
OUT
= 1:1
S
OUT
CLK
S
OUT
: PCLK = 8:1
CLK: S
OUT
= 1:2
S
OUT
CLK
CKEN Synchronously Disables Normal Parallel to Serial
Conversion
Synchronously Enables Normal Parallel to Serial Conversion
SYNC Asynchronously Resets Internal Flip−Flops* Synchronous Enable
*The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates
the conversion process synchronously on the next rising edge of CLK.
Table 3. INPUT VOLTAGE LEVEL SELECTION TABLE
Input Function Connect To V
CF
Pin
ECL Mode V
EF
Pin
CMOS Mode No Connect
TTL Mode* 1.5 V $ 100 mV
*For TTL Mode, if no external voltage can be provided, the reference
voltage can be provided by connecting the appropriate resistor
between V
CF
and V
EE
pins.
Table 4. DATA INPUT OPERATING VOLTAGE TABLE
Power Supply
(V
CC
,V
EE
)
Data Inputs (D [0:7])
CMOS TTL PECL NECL
PECL p p p N/A
NECL N/A N/A N/A p
Power Supply Resistor Value 10% (Tolerance)
3.3 V
1.5 kW
5.0 V
500 W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

MC10EP446FAG

Mfr. #:
Buy MC10EP446FAG
Manufacturer:
ON Semiconductor
Description:
Serial to Parallel Logic Converters 3.3V/5V ECL 8-Bit Serial to Parallel
Lifecycle:
New from this manufacturer.
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