MC10EP446, MC100EP446
http://onsemi.com
16
The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will
suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the
falling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resume
all activities (Figure 13).
Figure 13. Timing Diagram with CKEN with CKSEL HIGH
CLK
CKEN
SOUT
CKSEL
D1−1D0−1 D2−1 D3−1
PCLK
D4−1 D5−1
Disabled
Enabled
The differential PCLK output (Pins 14 and 15) is a word
framer and can help the user synchronize the serial data
output, S
OUT
(Pins 11 and 12), in their applications.
Furthermore, PCLK can be used as a trigger for input
parallel data (Figure 14).
An internally generated voltage supply, the V
BB
pin, is
available to this device only. For single–ended input
conditions, the unused differential input is connected to V
BB
as a switching reference voltage. V
BB
may also rebias AC
coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
should be left open. Also, both
outputs of the differential pair must be terminated (50 W to
V
TT
) even if only one output is used.
Figure 14. PCLK as Trigger Application
TRIGGER
Pattern Generator
Data Format Logic
(FPGA, ASIC)
PARALLEL
DATA OUTPUT
CLK
PCLK
EP446
PARALLEL
DATA INPUT
SYNC
S
OUT
SERIAL DATA
CLK RESET
