MC10EP446, MC100EP446
http://onsemi.com
12
APPLICATION INFORMATION
The MC10/100EP446 is an integrated 8:1 parallel to serial
converter. An attribute for EP446 is that the parallel inputs
D0–D7 (Pins 17 – 24) can be configured to accept either
CMOS, ECL, or TTL level signals by a combination of
interconnects between V
EF
(Pin 27) and V
CF
(Pin 26) pins.
For CMOS input levels, leave V
EF
and V
CF
open. For ECL
operation, short V
CF
and V
EF
(Pins 26 and 27). For TTL
operation, connect a 1.5 V supply reference to V
CF
and leave
the V
EF
pin open. The 1.5 V reference voltage to V
CF
pin can
be accomplished by placing a 1.5 kW or 500 W between V
CF
and V
EE
for 3.3 V or 5.0 V power supplies, respectively.
Note: all pins requiring ECL voltage inputs must have a
50 W terminating resistor to V
TT
(V
TT
= V
CC
– 2.0 V).
The CKSEL input (Pin 2) is provided to enable the user to
select the serial data rate output between internal clock data
rate or twice the internal clock data rate. For CKSEL LOW
operation, the time from when the parallel data is latched ¬
to when the data is seen on the S
OUT
is on the falling edge
of the 7
th
clock cycle plus internal propagation delay
(Figure 7). Note the PCLK switches on the falling edge of
CLK.
Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW
CLK
SOUT
PCLK
D0
D0−2
D1
D2
D3
D4
D5
D6
D7
D2−2
D3−2
D4−2
D5−2
D6−2
D7−2
D0−3
D1−3
D2−3
D3−3
D4−3
D5−3
D6−3
D7−3
D1−2
CKSEL
D0−1
D1−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D0−2
D1−2
D2−2
D3−2
D6−2
D0−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D1−1
D5−2
D0−4
D1−4
D2−4
D3−4
D4−4
D5−4
D6−4
D7−4
1234567
Number of Clock Cycles from Data Latch to SOUT
Data LatchedData Latched Data Latched Data Latched
D4−2
À
Á
