MC10EP446, MC100EP446
http://onsemi.com
14
The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip–flops and
clock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt serial
data bits are generated. The falling edge of the SYNC followed by a falling edge of CLK initiates the start of the conversion
process on the next rising edge of CLK (Figures 9 and 10). As shown in the figures below, the device will start to latch the
parallel input data after the a falling edge of SYNC ¬, followed by the falling edge CLK , on the next rising of edge of CLK
® for CKSEL LOW
Figure 9. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC
CLK
SYNC
SOUT
PCLK
D0
D0−2
D1
D2
D3
D4
D5
D6
D7
D2−2
D3−2
D4−2
D5−2
D6−2
D7−2
D0−3
D1−3
D2−3
D3−3
D4−3
D5−3
D6−3
D7−3
D1−2
CKSEL
D0−1
D1−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D0−2
D1−2
D2−2
D3−2
D4−2
D6−2
D0−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D1−1
D5−2
D0−4
D1−4
D2−4
D3−4
D4−4
D5−4
D6−4
D7−4
1234567
Data LatchedData Latched Data Latched Data Latched
Figure 10. Synchronous Release of SYNC for CKSEL LOW
CLK
SYNC
SYNC
(Asynchronous RESET)
À
Á
Â
À
Á
Â
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
