Philips Semiconductors Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
15
I
2
C Serial Interface
The I
2
C bus uses two wires (SDA and SCL) to transfer information
between devices connected to the bus. The main features of the
bus are:
• Bidirectional data transfer between masters and slaves.
• Serial addressing of slaves (no added wiring).
• Acknowledgment after each transferred byte.
• Multimaster bus.
• Arbitration between simultaneously transmitting masters without
corruption of serial data on bus.
The I
2
C subsystem includes hardware to simplify the software required
to drive the I
2
C bus. The hardware is a single bit interface which in
addition to including the necessary arbitration and framing error
checks, includes clock stretching and a bus timeout timer. The
interface is synchronized to software either through polled loops
or interrupts.
Refer to the application note AN422, entitled “Using the 8XC751
Microcontroller as an I
2
C Bus Master” for additional discussion of
the 8xC76x I
2
C interface and sample driver routines.
The P87LPC767 I2C implementation duplicates that of the 87C751
and 87C752 except for the following details:
• The interrupt vector addresses for both the I
2
C interrupt and the
Timer I interrupt.
• The I
2
C SFR addresses (I2CON, !2CFG, I2DAT).
• The location of the I
2
C interrupt enable bit and the name of the
SFR it is located within (EI2 is Bit 0 in IEN1).
• The location of the Timer I interrupt enable bit and the name of the
SFR it is located within (ETI is Bit 7 in IEN1).
• The I
2
C and Timer I interrupts have a settable priority.
Timer I is used to both control the timing of the I
2
C bus and also to
detect a “bus locked” condition, by causing an interrupt when
nothing happens on the I
2
C bus for an inordinately long period of
time while a transmission is in progress. If this interrupt occurs, the
program has the opportunity to attempt to correct the fault and
resume I
2
C operation.
Six time spans are important in I
2
C operation and are insured by timer I:
• The MINIMUM HIGH time for SCL when this device is the master.
• The MINIMUM LOW time for SCL when this device is a master.
This is not very important for a single-bit hardware interface like
this one, because the SCL low time is stretched until the software
responds to the I
2
C flags. The software response time normally
meets or exceeds the MIN LO time. In cases where the software
responds within MIN HI + MIN LO) time, timer I will ensure that
the minimum time is met.
• The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
• The MINIMUM SDA HIGH TO SDA LOW time between I
2
C stop
and start conditions (4.7ms, see I
2
C specification).
• The MINIMUM SDA LOW TO SCL LOW time in a start condition.
• The MAXIMUM SCL CHANGE time while an I
2
C frame is in
progress. A frame is in progress between a start condition and the
following stop condition. This time span serves to detect a lack of
software response on this device as well as external I
2
C
problems. SCL “stuck low” indicates a faulty master or slave. SCL
“stuck high” may mean a faulty device, or that noise induced onto
the I
2
C bus caused all masters to withdraw from I
2
C arbitration.
The first five of these times are 4.7 ms (see I
2
C specification) and
are covered by the low order three bits of timer I. Timer I is clocked
by the P87LPC767 CPU clock. Timer I can be pre-loaded with one
of four values to optimize timing for different oscillator frequencies.
At lower frequencies, software response time is increased and will
degrade maximum performance of the I
2
C bus. See special function
register I2CFG description for prescale values (CT0, CT1).
The MAXIMUM SCL CHANGE time is important, but its exact span
is not critical. The complete 10 bits of timer I are used to count out
the maximum time. When I
2
C operation is enabled, this counter is
cleared by transitions on the SCL pin. The timer does not run
between I
2
C frames (i.e., whenever reset or stop occurred more
recently than the last start). When this counter is running, it will carry
out after 1020 to 1023 machine cycles have elapsed since a change
on SCL. A carry out causes a hardware reset of the I
2
C interface
and generates an interrupt if the Timer I interrupt is enabled. In
cases where the bus hang-up is due to a lack of software response
by this device, the reset releases SCL and allows I
2
C operation
among other devices to continue.
Timer I is enabled to run, and will reset the I
2
C interface upon
overflow, if the TIRUN bit in the I2CFG register is set. The Timer I
interrupt may be enabled via the ETI bit in IEN1, and its priority set
by the PTIH and PTI bits in the Ip1H and IP1 registers respectively.
I
2
C Interrupts
If I
2
C interrupts are enabled (EA and EI2 are both set to 1), an I
2
C
interrupt will occur whenever the ATN flag is set by a start, stop,
arbitration loss, or data ready condition (refer to the description of ATN
following). In practice, it is not efficient to operate the I
2
C interface in
this fashion because the I
2
C interrupt service routine would somehow
have to distinguish between hundreds of possible conditions. Also,
since I
2
C can operate at a fairly high rate, the software may execute
faster if the code simply waits for the I
2
C interface.
Typically, the I
2
C interrupt should only be used to indicate a start
condition at an idle slave device, or a stop condition at an idle master
device (if it is waiting to use the I
2
C bus). This is accomplished by
enabling the I
2
C interrupt only during the aforementioned conditions.
Reading I2CON
RDAT The data from SDA is captured into “Receive DATa”
whenever a rising edge occurs on SCL. RDAT is also
available (with seven low-order zeros) in the I2DAT
register. The difference between reading it here and
there is that reading I2DAT clears DRDY, allowing the
I
2
C to proceed on to another bit. Typically, the first
seven bits of a received byte are read from
I2DAT, while the 8th is read here. Then I2DAT can be
written to send the Acknowledge bit and clear DRDY.
ATN “ATteNtion” is 1 when one or more of DRDY, ARL, STR, or
STP is 1. Thus, ATN comprises a single bit that can be
tested to release the I
2
C service routine from a “wait loop.”
DRDY “Data ReaDY” (and thus ATN) is set when a rising edge
occurs on SCL, except at idle slave. DRDY is cleared
by writing CDR = 1, or by writing or reading the I2DAT
register. The following low period on SCL is stretched
until the program responds by clearing DRDY.
