Philips Semiconductors Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
46
Additional Features
The AUXR1 register contains several special purpose control bits that
relate to several chip features. AUXR1 is described in Figure 37.
Software Reset
The SRST bit in AUXR1 allows software the opportunity to reset the
processor completely, as if an external reset or watchdog reset had
occurred. If a value is written to AUXR1 that contains a 1 at bit
position 3, all SFRs will be initialized and execution will resume at
program address 0000. Care should be taken when writing to
AUXR1 to avoid accidental software resets.
Dual Data Pointers
The dual Data Pointer (DPTR) adds to the ways in which the
processor can specify the address used with certain instructions.
The DPS bit in the AUXR1 register selects one of the two Data
Pointers. The DPTR that is not currently selected is not accessible
to software unless the DPS bit is toggled.
Specific instructions affected by the Data Pointer selection are:
INC DPTR Increments the Data Pointer by 1.
JMP @A+DPTR Jump indirect relative to DPTR value.
MOV DPTR, #data16 Load the Data Pointer with a 16-bit
constant.
MOVC A, @A+DPTR Move code byte relative to DPTR to the
accumulator.
MOVX A, @DPTR Move data byte the accumulator to data
memory relative to DPTR.
MOVX @DPTR, A Move data byte from data memory
relative to DPTR to the accumulator.
Also, any instruction that reads or manipulates the DPH and DPL
registers (the upper and lower bytes of the current DPTR) will be
affected by the setting of DPS. The MOVX instructions have limited
application for the P87LPC767 since the part does not have an
external data bus. However, they may be used to access EPROM
configuration information (see EPROM Characteristics section).
Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the
DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of
inadvertently altering other bits in the register.
BIT SYMBOL FUNCTION
AUXR1.7 KBF Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled for the Keyboard Interrupt
function goes low. Must be cleared by software.
AUXR1.6 BOD Brown Out Disable. When set, turns off brownout detection and saves power. See Power
Monitoring Functions section for details.
AUXR1.5 BOI Brown Out Interrupt. When set, prevents brownout detection from causing a chip reset and allows
the brownout detect function to be used as an interrupt. See the Power Monitoring Functions
section for details.
AUXR1.4 LPEP Low Power EPROM control bit. Allows power savings in low voltage systems. Set by software. Can
only be cleared by power-on or brownout reset. See the Power Reduction Modes section for
details.
AUXR1.3 SRST Software Reset. When set by software, resets the P87LPC767 as if a hardware reset occurred.
AUXR1.2 This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without
interfering with other bits in the register.
AUXR1.1 Reserved for future use. Should not be set to 1 by user programs.
AUXR1.0 DPS Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details.
DPS
SU01639
0SRSTLPEPBOIBODKBF
01234567
AUXR1
Reset Value: 00h
Not Bit Addressable
Address: A2h
Figure 37. AUXR1 Register
Philips Semiconductors Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
47
EPROM Characteristics
Programming of the EPROM on the P87LPC767 is accomplished
with a serial programming method. Commands, addresses, and data
are transmitted to and from the device on two pins after
programming mode is entered. Serial programming allows easy
implementation of in-circuit programming of the P87LPC767 in an
application board.
The P87LPC767 contains three signature bytes that can be read and
used by an EPROM programming system to identify the device. The
signature bytes designate the device as an P87LPC767 manufactured
by Philips. The signature bytes may be read by the user program at
addresses FC30h, FC31h and FC60h with the MOVC instruction,
using the DPTR register for addressing.
A special user data area is also available for access via the MOVC
instruction at addresses FCE0h through FCFFh. This “customer
code” space is programmed in the same manner as the main code
EPROM and may be used to store a serial number, manufacturing
date, or other application information.
32-Byte Customer Code Space
A small supplemental EPROM space is reserved for use by the
customer in order to identify code revisions, store checksums, add a
serial number to each device, or any other desired use. This area
exists in the code memory space from addresses FCE0h through
FCFFh. Code execution from this space is not supported, but it may
be read as data through the use of the MOVC instruction with the
appropriate addresses. The memory may be programmed at the
same time as the rest of the code memory and UCFG bytes are
programmed.
System Configuration Bytes
A number of user configurable features of the P87LPC767 must be
defined at power up and therefore cannot be set by the program after
start of execution. Those features are configured through the use of
two EPROM bytes that are programmed in the same manner as the
EPROM program space. The contents of the two configuration bytes,
UCFG1 and UCFG2, are shown in Figures 38 and 39. The values of
these bytes may be read by the program through the use of the
MOVX instruction at the addresses shown in the figure.
BIT SYMBOL FUNCTION
UCFG1.7 WDTE Watchdog timer enable. When programmed (0), disables the watchdog timer. The timer may
still be used to generate an interrupt.
UCFG1.6 RPD Reset pin disable. When 1 disables the reset function of pin P1.5, allowing it to be used as an
input only port pin.
UCFG1.5 PRHI Port reset high. When 1, ports reset to a high state. When 0, ports reset to a low state.
UCFG1.4 BOV Brownout voltage select. When 1, the brownout detect voltage is 2.5V. When 0, the brownout
detect voltage is 3.8V. This is described in the Power Monitoring Functions section.
UCFG1.3 CLKR Clock rate select. When 0, the CPU clock rate is divided by 2. This results in machine cycles
taking 12 CPU clocks to complete as in the standard 80C51. For full backward compatibility,
this division applies to peripheral timing as well.
UCFG1.2–0 FOSC2–FSOC0 CPU oscillator type select. See Oscillator section for additional information. Combinations
other than those shown below should not be used. They are reserved for future use.
FOSC2–FOSC0
Oscillator Configuration
1 1 1 External clock input on X1 (default setting for an unprogrammed part).
0 1 1 Internal RC oscillator, 6 MHz ±25%.
0 1 0 Low frequency crystal, 20 kHz to 100 kHz.
0 0 1 Medium frequency crystal or resonator, 100 kHz to 4 MHz.
0 0 0 High frequency crystal or resonator, 4 MHz to 20 MHz.
FOSC0
SU01185
FOSC1FOSC2CLKRBOVPRHIRPDWDTE
01234567
UCFG1
Unprogrammed Value: FFh
Address: FD00h
Figure 38. EPROM System Configuration Byte 1 (UCFG1)
Philips Semiconductors Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
48
BIT SYMBOL FUNCTION
UCFG2.7, 6 SB2, SB1 EPROM security bits. See table entitled, “EPROM Security Bits” for details.
UCFG2.5–0 Reserved for future use.
SU01186
SB1SB2
01234567
UCFG2
Unprogrammed Value: FFh
Address: FD01h
Figure 39. EPROM System Configuration Byte 2 (UCFG2)
Security Bits
When neither of the security bits are programmed, the code in the EPROM can be verified. When only security bit 1 is programmed, all further
programming of the EPROM is disabled. At that point, only security bit 2 may still be programmed. When both security bits are programmed,
EPROM verify is also disabled.
Table 12. EPROM Security Bits
SB2 SB1 Protection Description
1 1 Both security bits unprogrammed. No program security features enabled. EPROM is programmable and verifiable.
1 0 Only security bit 1 programmed. Further EPROM programming is disabled. Security bit 2 may still be programmed.
0 1 Only security bit 2 programmed. This combination is not supported.
0 0 Both security bits programmed. All EPROM verification and programming are disabled.
ABSOLUTE MAXIMUM RATINGS
PARAMETER RATING UNIT
Operating temperature under bias –55 to +125 °C
Storage temperature range –65 to +150 °C
Voltage on RST/V
PP
pin to V
SS
0 to +11.0 V
Voltage on any other pin to V
SS
–0.5 to V
DD
+0.5 V V
Maximum I
OL
per I/O pin 20 mA
Power dissipation (based on package heat transfer, not device power consumption) 1.5 W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification are not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.

P87LPC767FN,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 4KB OTP 20DIP
Lifecycle:
New from this manufacturer.
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