P87LPC767FN,112 Datasheet P87LPC767FN,112, P87LPC767BN,112, P87LPC767FD,512 | P22-P24

Philips Semiconductors Product data

P87LPC767

Low power, low price, low pin count (20 pin)

microcontroller with 4-kbyte OTP and 8-bit A/D converter

2002 Mar 25

Table 2. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER

SLAVEN,

MASTRQ,

MASTER

TIRUN OPERATING MODE

All 0 0

The I

C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I

application wants to ignore the I

C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero.

All 0 1 The I

C interface is disabled.

Any or all 1 0

The I

C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do

not, so that there is no checking for I

C being “hung.” This configuration can be used for very slow I

C operation.

Any or all 1 1

The I

C interface is enabled. Timer I runs during frames on the I

C, and is cleared by transitions on SCL, and by

Start and Stop conditions. This is the normal state for I

C operation.

Table 3. CT1, CT0 Values

CT1, CT0

Min Time Count

(Machine Cycles)

CPU Clock Max

(for 100 kHz I

Timeout Period

(Machine Cycles)

1 0 7 8.4 MHz 1023

0 1 6 7.2 MHz 1022

0 0 5 6.0 MHz 1021

1 1 4 4.8 MHz 1020

Interrupts

The P87LPC767 uses a four priority level interrupt structure. This

allows great flexibility in controlling the handling of the P87LPC767’s

many interrupt sources. The P87LPC767 supports up to 13 interrupt

sources.

Each interrupt source can be individually enabled or disabled by

setting or clearing a bit in registers IEN0 or IEN1. The IEN0

interrupts at once.

Each interrupt source can be individually programmed to one of four

priority levels by setting or clearing bits in the IP0, IP0H, IP1, and

IP1H registers. An interrupt service routine in progress can be

interrupted by a higher priority interrupt, but not by another interrupt

of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. So, if two

requests of different priority levels are received simultaneously, the

request of higher priority level is serviced.

If requests of the same priority level are received simultaneously, an

internal polling sequence determines which request is serviced. This

is called the arbitration ranking. Note that the arbitration ranking is

only used to resolve simultaneous requests of the same priority level.

Table 3 summarizes the interrupt sources, flag bits, vector

addresses, enable bits, priority bits, arbitration ranking, and whether

each interrupt may wake up the CPU from Power Down mode.

Table 4. Summary of Interrupts

Description

Interrupt

Flag Bit(s)

Vector

Address

Interrupt

Enable Bit(s)

Interrupt

Priority

Arbitration

Ranking

Power Down

Wakeup

External Interrupt 0 IE0 0003h EX0 (IEN0.0) IP0H.0, IP0.0 1 (highest) Yes

Timer 0 Interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1, IP0.1 4 No

External Interrupt 1 IE1 0013h EX1 (IEN0.2) IP0H.2, IP0.2 7 Yes

Timer 1 Interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3, IP0.3 10 No

Serial Port Tx and Rx TI & RI 0023h ES (IEN0.4) IP0H.4, IP0.4 12 No

Brownout Detect BOF 002Bh EBO (IEN0.5) IP0H.5, IP0.5 2 Yes

C Interrupt ATN 0033h EI2 (IEN1.0) IP1H.0, IP1.0 5 No

KBI Interrupt KBF 003Bh EKB (IEN1.1) IP1H.1, IP1.1 8 Yes

Comparator 2 interrupt CMF2 0043h EC2 (IEN1.2) IP1H.2, IP1.2 11 Yes

Watchdog Timer WDOVF 0053h EWD (IEN0.6) IP0H.6, IP0.6 3 Yes

A/D Converter ADCI 005Bh EAD (IEN1.4) IP1H.4, IP1.4 6 Yes

Comparator 1 interrupt CMF1 0063h EC1 (IEN1.5) IP1H.5, IP1.5 9 Yes

Timer I – 0073h ETI (IEN1.7) IP1H.7, IP1.7 13 (lowest) No

Philips Semiconductors Product data

P87LPC767

Low power, low price, low pin count (20 pin)

microcontroller with 4-kbyte OTP and 8-bit A/D converter

2002 Mar 25

External Interrupt Inputs

The P87LPC767 has two individual interrupt inputs as well as the

Keyboard Interrupt function. The latter is described separately

elsewhere in this section. The two interrupt inputs are identical to

those present on the standard 80C51 microcontroller.

The external sources can be programmed to be level-activated or

transition-activated by setting or clearing bit IT1 or IT0 in Register

TCON. If ITn = 0, external interrupt n is triggered by a detected low

at the INTn

pin. If ITn = 1, external interrupt n is edge triggered. In

this mode if successive samples of the INTn

pin show a high in one

cycle and a low in the next cycle, interrupt request flag IEn in TCON

is set, causing an interrupt request.

Since the external interrupt pins are sampled once each machine

cycle, an input high or low should hold for at least 6 CPU Clocks to

ensure proper sampling. If the external interrupt is

transition-activated, the external source has to hold the request pin

high for at least one machine cycle, and then hold it low for at least

one machine cycle. This is to ensure that the transition is seen and

that interrupt request flag IEn is set. IEn is automatically cleared by

the CPU when the service routine is called.

If the external interrupt is level-activated, the external source must

hold the request active until the requested interrupt is actually

generated. If the external interrupt is still asserted when the interrupt

service routine is completed another interrupt will be generated. It is

not necessary to clear the interrupt flag IEn when the interrupt is

level sensitive, it simply tracks the input pin level.

If an external interrupt is enabled when the P87LPC767 is put into

Power Down or Idle mode, the interrupt will cause the processor to

wake up and resume operation. Refer to the section on Power

Reduction Modes for details.

SU01401

WAKEUP

(IF IN POWER

DOWN)

(FROM IEN0

INTERRUPT

TO CPU

IE0

EX0

IE1

EX1

BOF

EBO

KBF

EKB

CM2

EC2

WDT

EWD

ADC

EAD

TF0

ET0

TF1

ET1

RI + TI

ATN

EI2

CM1

EC1

Figure 11. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources

Philips Semiconductors Product data

P87LPC767

Low power, low price, low pin count (20 pin)

microcontroller with 4-kbyte OTP and 8-bit A/D converter

2002 Mar 25

I/O Ports

The P87LPC767 has 3 I/O ports, port 0, port 1, and port 2. The

exact number of I/O pins available depend upon the oscillator and

reset options chosen. At least 15 pins of the P87LPC767 may be

used as I/Os when a two-pin external oscillator and an external

reset circuit are used. Up to 18 pins may be available if fully on-chip

oscillator and reset configurations are chosen.

All but three I/O port pins on the P87LPC767 may be software

configured to one of four types on a bit-by-bit basis, as shown in

Table 4. These are: quasi-bidirectional (standard 80C51 port

outputs), push-pull, open drain, and input only. Two configuration

registers for each port choose the output type for each port pin.

Table 5. Port Output Configuration Settings

PxM1.y PxM2.y Port Output Mode

0 0 Quasi-bidirectional

0 1 Push-Pull

1 0 Input Only (High Impedance)

1 1 Open Drain

Quasi-Bidirectional Output Configuration

The default port output configuration for standard P87LPC767 I/O

ports is the quasi-bidirectional output that is common on the 80C51

and most of its derivatives. This output type can be used as both an

input and output without the need to reconfigure the port. This is

possible because when the port outputs a logic high, it is weakly

driven, allowing an external device to pull the pin low. When the pin

is pulled low, it is driven strongly and able to sink a fairly large

current. These features are somewhat similar to an open drain

output except that there are three pull-up transistors in the

quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the “very weak” pull-up, is turned on

whenever the port latch for the pin contains a logic 1. The very weak

pull-up sources a very small current that will pull the pin high if it is

left floating.

A second pull-up, called the “weak” pull-up, is turned on when the

port latch for the pin contains a logic 1 and the pin itself is also at a

logic 1 level. This pull-up provides the primary source current for a

quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1

on it is pulled low by an external device, the weak pull-up turns off,

and only the very weak pull-up remains on. In order to pull the pin

low under these conditions, the external device has to sink enough

current to overpower the weak pull-up and take the voltage on the

port pin below its input threshold.

The third pull-up is referred to as the “strong” pull-up. This pull-up is

used to speed up low-to-high transitions on a quasi-bidirectional port

pin when the port latch changes from a logic 0 to a logic 1. When this

occurs, the strong pull-up turns on for a brief time, two CPU clocks, in

order to pull the port pin high quickly. Then it turns off again.

The quasi-bidirectional port configuration is shown in Figure 12.

SU01159

WEAK

VERY

WEAK

STRONG

PORT

2 CPU

CLOCK DELAY

INPUT

DATA

PORT LATCH

DATA

PPP

Figure 12. Quasi-Bidirectional Output

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P87LPC767FN,112

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IC MCU 8BIT 4KB OTP 20DIP

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P87LPC767FN,112

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