RL78/G10 CHAPTER 2 ELECTRICAL SPECIFICATIONS
R01DS0207EJ0100 Rev.1.00
Apr 15, 2013
Page 18 of 28
(2) CSI mode (master mode, SCKp... internal clock output)
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 200
ns SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK
2.0 V ≤ V
DD ≤ 5.5 V 800 ns
2.7 V ≤ VDD ≤ 5.5 V
t
KCY1
/2-18
ns SCKp high-/low-level width tKH1, tKL1
2.0 V ≤ V
DD ≤ 5.5 V
t
KCY1
/2-50
ns
2.7 V ≤ VDD ≤ 5.5 V 47 ns SIp setup time (to SCKp↑)
Note 1
tSIK1
2.0 V ≤ V
DD ≤ 5.5 V 110 ns
SIp hold time (from SCKp↑)
Note 2
tKSI1 19 ns
Delay time from SCKp↓ to SOp
output
Note 3
t
KSO1 C = 30 pF
Note 4
25 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Remarks 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0)
2. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
