RL78/G10 CHAPTER 2 ELECTRICAL SPECIFICATIONS
R01DS0207EJ0100 Rev.1.00
Apr 15, 2013
Page 19 of 28
(3) CSI mode (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fMCK = 20 MHz 8/fMCK ns 2.7 V ≤ VDD ≤ 5.5 V
f
MCK ≤ 10 MHz 6/fMCK ns
SCKp cycle time tKCY2
2.0 V ≤ V
DD < 2.7 V 6/fMCK ns
SCKp high-/low-level width tKH2,
t
KL2
2.0 V ≤ V
DD ≤ 5.5 V tKCY2/2 ns
2.7 V ≤ VDD ≤ 5.5 V
1/f
MCK +
20
ns
SIp setup time (to SCKp↑)
Note 1
tSIK2
2.0 V ≤ V
DD < 2.7 V
1/f
MCK +
30
ns
SIp hold time (from SCKp↑)
Note 2
tKSI2 2.0 V ≤ VDD ≤ 5.5 V
1/f
MCK +
31
ns
2.7 V ≤ VDD ≤ 5.5
V
2/f
MCK + 50 ns
Delay time from SCKp↓ to SOp
output
Note 3
t
KSO2 C = 30 pF
Note 4
2.0 V ≤ V
DD < 2.7
V
2/f
MCK + 110 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
Remarks 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0)
2. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (mn = 00))
