AD6620
–21–REV. A
The frequency of the SYNC_NCO pulses, and therefore the
accuracy of the synchronization, is determined by the value of
the NCO Sync Control Register at address 302 hex. The value
in this register is the SYNC_MASK and is interpreted as a
32-bit unsigned integer. This value controls the window around
the zero crossing of the NCO output sine wave in which the
NCO will output a SYNC_NCO pulse as a master. As a slave,
the value in this register will determine the number of MSBs
of the output sine wave that are synchronized with the master.
The Master and all slaves should use the same SYNC_MASK
word. This value should almost always be written as all 1s
(FFFFFFFF hex).
Effects of A/B Input on the NCO
If the AD6620 is run in Single Channel Real mode using frac-
tional rate input timing, the A/B input is used to enable the
NCO advancement. If the A/B line is held high longer than one
clock period, the NCO will advance for each rising edge of the
CLK while A/B is high. This is not normally the desired result
and thus A/B must be taken low after the first CLK period to
prevent anomalous NCO results. See additional details under
Fractional Rate Timing.
Phase Continuous Tuning with the AD6620
For synchronization purposes, the AD6620 NCO phase is reset
each time the NCO frequency register is either written to or
read from. This is accomplished by forcing an NCO Sync to
occur. Normally, phase-continuous tuning is required on the
transmit path to control spectral leakage. On the receive path
this in not usually a constraint. However, if phase-continuous
tuning is required with the AD6620, it can be accomplished by
configuring the AD6620 as a Sync Slave. In this manner, no
internal NCO sync is generated when the NCO frequency regis-
ter is written to. If multiple AD6620s are synchronized together,
a common external sync pulse can be used to lock each of the
receivers together at the appropriate point in time. It is also
possible to reconfigure the AD6620 after the NCO frequency
register has been written so that the chip is once again a Sync
Master. The next time the NCO phase cycles through 0 degrees,
the NCO sync is exerted and the chip is again synchronized.
2ND ORDER CASCADED INTEGRATOR COMB FILTER
The CIC2 filter is a fixed-coefficient, decimating filter. It is
constructed as a second order CIC filter whose characteristics
are defined only by the decimation rate chosen. This filter can
process signals at the full rate of the input port (67 MHz) in all
input modes. The output rate of this stage is given by the equa-
tion below.
f
f
M
SAMP
SAMP
CIC
2
2
=
The decimation ratio, MCIC2, is an unsigned integer that may
be between 1 and 16. This stage may be bypassed under certain
conditions by setting, M
CIC2
equal to 1. For this to happen the
processing clock rate, f
CLK
must be two or more times the input
data rate, f
SAMP
. This is because the I and Q data is processed in
parallel within the CIC2 filter, and the I and Q output data is
then multiplexed through the same data pipe before it enters the
CIC5 filter.
The frequency response of the CIC2 filter is given by the follow-
ing equations.
Hz
z
z
S
M
CIC
CIC
()
1
2
1
1
2
2
1
2
Hf
Mf
f
f
f
S
CIC
SAMP
SAMP
CIC
()
sin
sin
×
1
2
2
2
2
π
π
The scale factor, S
CIC2
is a programmable unsigned integer
between 0 and 6. This serves as an attenuator that can reduce
the gain of the CIC2 in 6 dB increments. For the best dynamic
range, S
CIC2
should be set to the smallest value possible (i.e.,
lowest attenuation) without creating an overflow condition.
This can be safely accomplished using the equation below, where
input_level is the largest fraction of full scale possible at the
input to this AD6620 (normally 1). The CIC2 scale factor is
not ignored when the CIC2 is bypassed.
REGISTER
REGISTER
1
MASKED
COUNT = 0?
SYNC
MASK
SYNC_NCO
PIN
1
1
32
32
32
32
1
0
32
32
32
32
32
NCO
FREQ
AMPLITUDE
DITHER
COS
SIN
PHASE
DITHER
PHASE
OFFSET
PHASE
ACCUMULATOR
X4
REGISTER
Figure 35. NCO Block Diagram
AD6620
–22–
REV. A
S ceil M input level
OL input level
CIC CIC
CIC
S
CIC
222
2
2
1
2
2
log ( _ )
_
The equations for calculating CIC2 output level is correct when
stage is not bypassed (normal operation). However, when by-
passed, the following equations should be used instead.
OL
CIC2
= Input Level
The gain and pass band droop of the CIC2 should be calculated
by the equations above, as well as the filter transfer equations
that follow. If these are unacceptable, they can be compensated
for in subsequent stages.
CIC2 Rejection
The table below illustrates the amount of bandwidth in percent
of the data rate into the CIC2 stage. The data in this table may
be scaled to any allowable sample rate up to 67 MHz in Single
Channel Mode or 33.5 MHz in Diversity Channel Mode. The
table can be used as a tool to decide how to distribute the deci-
mation between CIC2, CIC5 and the RCF.
The data in this table may be scaled to any allowable sample
rate up to 67 MHz in Single Channel Mode or 33.5 MHz in
Diversity Channel Mode.
Table III. SSB CIC2 Alias Rejection Table (f
SAMP
= 1)
Bandwidth Shown in Percentage of f
SAMP
M
CIC2
–50 dB –60 dB –70 dB –80 dB –90 dB –100 dB
2 1.79 1.007 0.566 0.318 0.179 0.101
3 1.508 0.858 0.486 0.274 0.155 0.087
4 1.217 0.696 0.395 0.223 0.126 0.071
5 1.006 0.577 0.328 0.186 0.105 0.059
6 0.853 0.49 0.279 0.158 0.089 0.05
7 0.739 0.425 0.242 0.137 0.077 0.044
8 0.651 0.374 0.213 0.121 0.068 0.038
9 0.581 0.334 0.19 0.108 0.061 0.034
10 0.525 0.302 0.172 0.097 0.055 0.031
11 0.478 0.275 0.157 0.089 0.05 0.028
12 0.439 0.253 0.144 0.082 0.046 0.026
13 0.406 0.234 0.133 0.075 0.043 0.024
14 0.378 0.217 0.124 0.07 0.04 0.022
15 0.353 0.203 0.116 0.066 0.037 0.021
16 0.331 0.19 0.109 0.061 0.035 0.02
Example Calculations
Goal: Implement a filter with an Input Sample Rate of 10 MHz
requiring 100 dB of Alias Rejection for a ±7 kHz pass band.
Solution: First determine the percentage of the sample rate that
is represented by the pass band.
BW
kHz
MHz
FRACTION
=× =100
7
10
007.%
Find the 100 dB column on the right of the table and look
down this column for a value greater than or equal to your
pass band percentage of the clock rate. Then look across to the
extreme left column and find the corresponding decimation
rate. Referring to the table, notice that for a decimation of 4, the
frequency having 100 dB of alias rejection is 0.071 percent
which is slightly greater than the 0.07 percent calculated. There-
fore, the maximum bound on CIC2 decimation for this condi-
tion is four. Additional decimation means less alias rejection
than the 100 dB required.
Note that although an M
CIC2
less then four would still yield the
required rejection, overall power consumption is reduced by
decimating as much as possible in this stage. Decimation in
CIC2 lowers the data rate and thus reduces power consumed in
subsequent stages.
The plot below shows the CIC2 transfer function using a deci-
mation of four. The first plot is referenced to the input sample
rate, the complex spectrum from f
SAMP
/2 to f
SAMP
/2. The sec-
ond plot is referenced to the CIC2 output rate, the complex
spectrum from f
SAMP2
/2 to f
SAMP2
/2. The aliases of the CIC2
can be seen to be folding back in toward the edge of the
desired filter pass band. It is the level of these aliases as they
move into the desired pass band that are important.
0.5
120
100
80
60
40
20
0
dBFS
f/f
SAMP
0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.50
0.5
120
100
80
60
40
20
0
dBFS
f/f
SAMP2
0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.50
Figure 36. CIC2 Alias Rejection, M
CIC2
= 4
The set of plots below show a decimation of 16 in the CIC2
filter. The lobes of the filter drop as the decimation rate
increases, but the amplitudes of the aliased frequencies increase
because the output rate has been reduced.
AD6620
–23–REV. A
The frequency response of the filter is given by the following
equations. The gain and pass band droop of CIC5 should be
calculated by these equations. Both parameters may be compen-
sated for in the RCF stage.
Hz
z
z
S
M
CIC
CIC
()
+
1
2
1
1
5
5
51
5
Hf
Mf
f
f
f
S
CIC
SAMP
SAMP
CIC
()
sin
sin
×
+
1
2
5
5
5
2
2
5
π
π
The scale factor, S
CIC5
is a programmable unsigned integer
between 0 and 20. It serves to control the attenuation of the
data into the CIC5 stage in 6 dB increments. For the best dynamic
range, S
CIC5
should be set to the smallest value possible (lowest
attenuation) without creating an overflow condition. This can
be safely accomplished using the equation below, where OL
CIC2
is the largest fraction of full scale possible at the input to this
filter stage. This value is output from the CIC2 stage then pipe-
lined into the CIC5. S
CIC5
is ignored when this filter is bypassed
by setting M
CIC5
= 1.
S ceil M OL
OL
M
OL
CIC CIC CIC
CIC
CIC
S
CIC
CIC
525
5
2
5
5
5
5
2
5
2
5
()
=
()
×
+
log ( )
when CIC5 is bypassed;
OL OL
CIC CIC52
=
The output rate of this stage is given by the equation below.
f
f
M
SAMP
SAMP
CIC
5
2
5
0.5
120
100
80
60
40
20
0
dBFS
f/f
SAMP
0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.50
0.5
120
100
80
60
40
20
0
dBFS
f/f
SAMP2
0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.50
Figure 37. CIC2 Alias Rejection, M
CIC2
= 16
5TH ORDER CASCADED INTEGRATOR COMB FILTER
The third signal processing stage, CIC5, implements a sharper
fixed-coefficient, decimating filter than CIC2. The input rate to
this filter is f
SAMP2
. The maximum input rate is given by the
equation below. N
CH
equals two for Diversity Channel Real
input mode; otherwise N
CH
equals one. In order to satisfy this
equation, M
CIC2
can be increased, N
CH
can be reduced, or f
CLK
can be increased (reference fractional rate input timing described
in the Input Timing section).
f
f
N
SAMP
CLK
CH
2
2
×
The decimation ratio, M
CIC5
, may be programmed from 1 to 32
(all integer values). When M
CIC5
= 1, this stage is bypassed and
the CIC5 scale factor is ignored.

AD6620ASZ

Mfr. #:
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Analog Devices Inc.
Description:
Up-Down Converters 65MSPS Digital Rcvr Signal Processor
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