AD6620
–42–
REV. A
PARALLEL PROCESSING USING AD6620
If a single AD6620 does not have enough time to compute an
adequate filter, multiple AD6620s can be operated in parallel as
shown in Figure 56. In this example, the processing is distrib-
uted between four chips so that each chip can process more
taps. The outputs are then combined such that the desired data
rate is achieved.
CLK
D
IN
SYNC RCF
D
OUT
DV
OUT
AD6620 #1
AIN
ENCODE
CLOCK
CLK
D
IN
SYNC RCF
D
OUT
DV
OUT
AD6620 #2
CLK
D
IN
SYNC RCF
D
OUT
DV
OUT
AD6620 #4
CLK
D
IN
SYNC RCF
D
OUT
DV
OUT
AD6620 #3
LATCH
OUTPUT
SELECTOR
RCF TIMING
CONTROL
AD6640
Figure 56. Parallel Processing with the AD6620
In this application, one high speed ADC can feed parallel
AD6620s. Although not shown in this diagram, the SYNC_NCO
and SYNC_CICs are tied together and synchronized from an
external source with all chips run as SYNC_Slaves.
This architecture allows for each AD6620 to process four times
as many taps as would otherwise be possible. Consider the
example of an ADC clocked at 58.9824 MHz and a desired
output data rate of 4.9152 MHz. If a single AD6620 were used,
the decimation rate would be 12 (58.9824/4.9152) allowing for
only 12 taps in the FIR filter. Not nearly enough for a usable
digital filter. Now consider the case where each AD6620 only
provides an output for one in four samples. In this case, the
decimation rate per chip would be four times larger, 48 in this
example. With a decimation of 48, more taps for the filter can
be generated and produce a much better filter.
COUNTER
0 TO 47
CLOCK IN
COUNT = 0
COUNT = 11
COUNT = 23
COUNT = 35
Figure 57. RCF Timing Generator for Parallel Processing
Implementation of such a procedure is quite simple and basi-
cally shown in Figure 57. The filter design would proceed by
designing the filter to have the desired spectral characteristics
at its output rate. For our example here, each AD6620 would
have an output rate of 1.2288 MHz. The filter should be designed
such that the required rejection is attained directly at this rate.
This one filter is loaded into each chip. Upsampling is achieved
on the output by multiplexing between the different AD6620
outputs which are staggered, in this case by 90 degrees of the
output data rate. Therefore, since the decimation rate is 48
and four AD6620s are used, every 12 high speed clock cycles
a new AD6620 output should be selected. The most direct
method is to use these pulses to trigger the SYNC_RCF signals.
This staggering is required to properly phase the AD6620’s inter-
nal computations. Once the chips have been synchronized in this
manner, they will begin producing DV
OUT
signals that can be
used to instruct the Output Selector which output is valid.
The RCF Timing Control is responsible for proper phasing of
the AD6620s in the system. The example shown here is for the
example of four devices in parallel. It can easily be expanded to
any number of devices with this methodology. Since the AD6620s
are decimating by 48, the complete cycle time is 48 system
clocks. Thus the timing control must run modulo 48. When the
count is 0, the first RCF should be reset with a pulse that is one
clock cycle wide. Likewise, when the count is 11, 23 and 35,
RCF2, RCF3 and RCF4 should be reset respectively. This will
properly phase the AD6620s to run 90 degrees out of phase. If
this example consisted of six AD6620s, then they should be
reset on count 0, 7, 15, 23, 31 and 39. Following this method,
any number of AD6620s can be paralleled for higher data rates.
Once the AD6620 RCFs are properly phased, the DV
OUT
signals
will then enable the output selector to know which outputs should
be connected at the correct point in time. In review, the DV
OUT
signal pulses high when the RCF data is being placed on the out-
puts. Since the devices are operated in Single Channel Real
mode, this signal will be high for two clock cycles while two
pieces of data are written to the output. The output pairs consist
of I followed by Q. As each chip’s DV
OUT
cycles high, its data
should be connected to the output bus as shown below. This
effectively forms a MUX that sequentially cycles the output of
each of the AD6620s in the system to the output port. The only
remaining issue is retiming the data. Since each AD6620 clocks its
data out in two clock cycles, there will be 10 cycles where the
data is idle. During this period, the last Q out will remain valid
until the next chip in the sequence generates its DV
OUT
signal. This
normally should pose no problem, but if it does, the output data
could easily go to a FIFO and be retimed so that output data
streams at a regular rate.
In order to meet conventional logic requirements, OE for each
of the input latches should be active low. The DV
OUT
of the
AD6620 is active high, therefore, an inverter must be typically
inserted between the DV
OUT
lines and the OE of the latches as
shown in the updated Figure 58.
