AD6620ASZ Datasheet AD6620ASZ, AD6620ASZ-REEL | P31-P33

AD6620

–30–

REV. A

PROGRAMMING THE AD6620

Initializing the AD6620

Before the AD6620 can be used to down convert and filter the

channel of interest it must be configured for the job. First the

RESET pin should be pulsed low for a minimum of 30 ns and

should then be returned high. This HARD_RESET of the

AD6620 clears the CIC Accumulators as well as the NCO

Phase Accumulator. When RESET is brought high the AD6620 is

removed from the HARD_RESET condition. The AD6620 is

now in SOFT_RESET. In this state the Mode Control Register

at address 0x300 contains a “1” (Bit 0 is high). When the AD6620

is in SOFT_RESET, no data is accepted by the input data port

and no processing occurs. The serial port and parallel output

port is held inactive and the chip is defined as a SYNC slave to

avoid possible contentions on these pins. While the AD6620 is

in this condition it should be programmed by the process below.

It should be noted that this initialization must be performed via

the microprocessor port since the serial port is inactive.

1. If the AD6620 is being reinitialized without performing a

HARD_RESET, then address 0x300 should be written 1 to

place the AD6620 in SOFT_RESET. This allows the non-

dynamic registers to be programmed.

2. Program the Coefficient RAM of the AD6620 with the

desired FIR Filter. The address auto-increment feature can

be used to decrease the amount of time required to program

the Coefficients. This feature is described in detail in the

Microport Control section that follows.

3. (Optional) The first piece of data out of the AD6620 is always

zero due to an output pipeline delay. There will also be a

start-up glitch on the output of the AD6620 due to possible

nonzero data in the I and Q data RAMS of the RCF filter.

These RAMS are not initialized by the HARD_RESET. If

this is a concern then the data RAMS should now be written

to zero. For efficiency the auto-increment feature can be

used as with the programming of the coefficient RAMs.

4. The Configuration Registers of the AD6620 are now pro-

grammed. First, address 0x300 should be written to set the

Operating Mode if Diversity Channel Real or Single Channel

Complex Modes are used. Bit 0 of this register should remain

high at this time. This will hold the SOFT_RESET condition.

The remaining configuration registers can now be programmed.

This should start at address 0x301 and continue to address

0x30D. This defines the operation of the NCO and filter stages.

5. The AD6620 is now ready to be removed from SOFT_RESET

and allowed to process data. This is done by writing address

0x300 to again set the desired mode of operation. This loca-

tion should be set for SYNC MASTER or SYNC SLAVE

operation at this time. Bit 0 of this register is written low at

this time to remove the SOFT_RESET condition.

Dynamic Programming of the AD6620

Many attributes of the AD6620 may be altered dynamically as

the AD6620 processes the received data. This allows the receiver

to be adjusted during operation in order to achieve the maxi-

mum performance. The typical dynamic registers of the AD6620

are listed in the following table. To program the other registers

follow the steps described in the section titled Initializing the

AD6620. Technically all registers can be programmed dynami-

cally, but adverse results may occur if registers other those listed

are written dynamically.

These addresses may be programmed via either the Micropro-

cessor or the Serial Control Ports.

Table X. Dynamic AD6620 Registers

Address Bit Width Name

302 32 NCO SYNC CONTROL REGISTER

303 32 NCO_FREQ

304 16 NCO PHASE_OFFSET

305 8 INPUT/CIC2 SCALE REGISTER

307 5 CIC5 SCALE REGISTER

309 4 OUTPUT/RCF CONTROL REGISTER

30B 8 RCF ADDRESS OFFSET REGISTER

Registers 0x302, 0x303 and 0x304 allow the NCO of the AD6620

to be adjusted. The tuning frequency can be dynamically changed

for frequency hopping. The phase of the carrier can be adjusted

with address 0x304. The phase accuracy of the synchronization

can be changed with 0x302. Registers 0x305, 0x307, and 0x309

allow the user to dynamically control the gain of the AD6620 in

6 dB increments. This can be used to maximize the AD6620s

dynamic range for the signal being tuned at a particular instant.

spectral estimation.

In addition to dynamically writing to these registers, they may

also be read to verify program content. Care should be taken,

however, because reading some registers may affect normal chip

operation. In particular, reading from 303h the NCO frequency

will cause the phase accumulator to be reset via the SYNC_NCO

pulse if the AD6620 is running as a Sync master. If the device is

run as a Sync slave, then the phase accumulator is not reset.

Addresses 000h through 1FFh should not be read dynamically

as doing so will disrupt the internal state machine computing

the FIR taps. These locations may be read statically if needed.

AD6620

–31–REV. A

ACCESS PROTOCOLS

The AD6620 external accesses may be performed through either

the Microprocessor Port or the Serial Port. The Microport and

the serial port both use a three-bit address and eight-bit data to

access these registers. The three-bit address provides access to

seven register locations (External Interface Registers). These

the AD6620 shown in the Control Register section. The seven

registers are the LAR (Low Address Register), the AMR (Address

Mode Register), and the five data registers (DR4–DR0).

Table XI. External Interface Registers

A[2:0] Name Comment

000 Data Register 0 (DR0) D[7:0]

001 Data Register 1 (DR1) D[15:8]

010 Data Register 2 (DR2) D[23:16]

011 Data Register 3 (DR3) D[31:24]

100 Data Register 4 (DR4) D[35:32]

101 Reserved Reserved

110 Low Address Register (LAR) A[7:0]

111 Address Mode Register (AMR) 1-0: A[9:8]

5-2: Reserved

6: Read Increment

7: Write Increment

The internal address space is accessed using a 10-bit internal

address. Many of these address locations are more than a byte

wide and require multiple accesses to the seven External Inter-

face Registers, which are each only 8 bits wide (only 4 bits of

DR4 are used). Accesses to these registers are accomplished

using the 3-bit address and 8-bit data lines the manner described

below. The source of these values depends on the control port

method used.

All internal accesses are accomplished by first writing the inter-

nal address of the register or memory location to be accessed.

The lower eight address bits are written to the LAR register

and the upper two address bits to the LSBs of the AMR. This

defines the internal address of the location to be accessed as

shown in the memory map shown in the Control Registers and

On-Chip RAM section.

Internal Write Access

Up to 36 bits of data (as needed) can be written by the process

described below. Any high order bytes that are needed are writ-

ten to the corresponding data registers defined in the external

3-bit address space. The least significant byte is then written to

DR0 at address (000). When a write to DR0 is detected, the

internal microprocessor port state machine then moves the data

in DR4–DR0 to the internal address pointed to by the address

in the LAR and AMR.

Write Pseudocode

void write_micro(ext_address, int data);

main();

{

/* This code shows the programming of the NCO frequency

variable address is the External Address A[2:0] and data is the

value to be placed in the external interface register. The NCO

// holding registers for NCO byte wide access data

int d3, d2, d1, d0;

// NCO frequency word (32-bits wide)

NCO_FREQ = 0xCBEFEFFF;

// write AMR

write_micro(7, 0x03);

// write LAR

write_micro(6, 0x03);

// DR4 is not needed because NCO_FREQ is only 32-bits, not

// write DR3 with high byte of 32 bit word (D[31:24]

d3 = (NCO_FREQ & 0xFF000000) >> 24;

write_micro(3, d3);

// write DR2 with high byte of 32 bit word (D[23:16]

d2 = (NCO_FREQ & 0xFF0000) >> 16;

write_micro(2, d2);

// write DR1 with D[15:8]

d1 = (NCO_FREQ & 0xFF00) >> 8;

write_micro(1, d1);

// write DR0 with D[7:0]

// Writing to DR0 causes all data to be transferred to the

internal address.

//Therefore, DR1, DR2 and DR3 should already be written

d0 = NCO_FREQ & 0xFF;

write_micro(0, d0);

} // end of main

Internal Read Access

A read is performed by first writing the LAR and AMR as with a

write. The data registers (DR4–DR0) are then read in the reverse

order that they were written. First, the least significant byte of

the data (D[7:0]) is read from DR0. On this transaction the

high bytes of the data are moved from the internal address

pointed to by the LAR and AMR into the remaining data regis-

ters (DR4–DR1). This data can then be read from the data

registers using the appropriate 3-bit addresses. The number of

data registers used depends solely on the amount of data to be

read or written. Any unused bit in a data register should be

masked out for a read.

AD6620

–32–

REV. A

Read Pseudocode

int read_micro(ext_address);

main();

{

/* This code shows the reading of the NCO frequency register

using the read_micro function as defined above. The variable

address is the External Address A[2..0] and data is the value to

be placed in the external interface register. The NCO register is

located at Internal Address = 0x303.

// holding registers for NCO byte wide access data

int d3, d2, d1, d0;

// NCO frequency word (32-bits wide)

// write AMR

write_micro(7, 0x03 );

// write LAR

write_micro(6, 0x03);

/* read D[7:0] from DR0, All data is moved from the Internal

Registers to the interface registers on this access. Reading

should be initiated with a read from DR0. Therefore, DR1,

DR2 and DR3 can be read after DR0 */

d0 = read_micro(0) & 0xFF;

// read D[15:8] from DR1

d1 = read_micro(1) & 0xFF;

// read D[23:16] from DR2

d2 = read_micro(2) & 0xFF;

// read D[31:24] from DR3

d3 = read_micro(3) & 0xFF;

// DR4 is not needed because NCO_FREQ is only 32-bits

// Assemble 32-bit NCO_FREQ word from the 4 byte

components

NCO_FREQ = d0 + (d1 << 8) + (d2 << 16) + (d3 << 24);

} // end of main

Auto Increment Feature

To increase throughput, an auto increment feature is provided.

This feature is controlled by Bits 6 and 7 of the AMR. If these

bits are set to 00, the address remains the same after an internal

access. If set to 01, the address is incremented after a read access

has been performed. If set to 10, the address is incremented

after a write access is performed. If set to 11, the address is incre-

mented after each access, read or write. This allows the AD6620

to be initialized in a much shorter time since the access to the

LAR and AMR must occur only once to initialize or read-back

the entire device.

MICROPORT CONTROL

External reads and writes are accomplished in one of two modes

via the Microprocessor Port. The CS, RD (DS), RDY (DTACK),

WR (R/W) and MODE pins are used to control the access. The

specific function of these pins depends on whether the access is

MODE 0 or MODE 1. The Mode 1 signal names are those

listed on the pinout. The access mode is controlled by the

MODE input as described in the following sections.

Table XII. Microprocessor Control Signals

MODE 0 MODE 1

A[2:0] (Address Lines) A[2:0] (Address Lines)

D[7:0] (Data Lines) D[7:0] (Data Lines)

CS (Chip Select) CS (Chip Select)

RD (Read Strobe) DS (Data Strobe)

WR (Write Strobe) R/W (Read/Write Select)

RDY (Ready Signal) DTACK (Data Acknowledge)

MODE (Mode Select) MODE (Mode Select)

The Microport is synchronous with the master clock (CLK) of

the AD6620, but the interface is not required to be. If the speed

of the interface is significantly slower than CLK, synchronicity

should not be an issue. If the interface is relatively fast com-

pared to CLK, the user may need to synchronize the Microport

to CLK or add wait states to the controlling processor. The

timing diagrams show the relationship of the control signals to

clock and the user should use these as a guide to implement a

Microport interface.

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AD6620ASZ

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Up-Down Converters 65MSPS Digital Rcvr Signal Processor

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AD6620ASZ

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