–5–REV. A
AD6620
TIMING CHARACTERISTICS
(C
LOAD
= 40 pF All Outputs)
Test AD6620AS
Parameter (Conditions) Temp Level Min Typ Max Unit
CLK Timing Requirements:
t
CLK
CLK Period Full I 14.93
1
ns
t
CLK
CLK Period Full I 15.4 ns
t
CLKL
CLK Width Low Full IV 7.0 0.5 × t
CLK
ns
t
CLKH
CLK Width High Full IV 7.0 0.5 × t
CLK
ns
Reset Timing Requirements:
t
RESL
RESET Width Low Full I 30.0 ns
Input Data Timing Requirements:
t
SI
Input
2
to CLK Setup Time Full IV –1.0 ns
t
HI
Input
2
to CLK Hold Time Full IV 6.5 ns
Parallel Output Switching Characteristics:
t
DPR
CLK to OUT[15:0] Rise Delay Full IV 8.0 19.5 ns
t
DPF
CLK to OUT[15:0] Fall Delay Full IV 7.5 19.5 ns
t
DPR
CLK to DV
OUT
Rise Delay Full IV 6.5 19.0 ns
t
DPF
CLK to DV
OUT
Fall Delay Full IV 5.5 11.5 ns
t
DPR
CLK to IQ
OUT
Rise Delay Full IV 7.0 19.5 ns
t
DPF
CLK to IQ
OUT
Fall Delay Full IV 6.0 13.5 ns
t
DPR
CLK to AB
OUT
Rise Delay Full IV 7.0 19.5 ns
t
DPF
CLK to AB
OUT
Fall Delay Full IV 5.5 13.5 ns
SYNC Timing Requirements:
t
SY
SYNC
3
to CLK Setup Time Full IV –1.0 ns
t
HY
SYNC
3
to CLK Hold Time Full IV 6.5 ns
SYNC Switching Characteristics:
t
DY
CLK to SYNC
4
Delay Time Full V 7.0 23.5 ns
Serial Input Timing:
t
SSI
SDI to SCLKt Setup Time Full IV 1.0 ns
t
HSI
SDI to SCLKt Hold Time Full IV 2.0 ns
t
HSRF
SDFS to SCLKu Hold Time Full IV 4.0 ns
t
SSF
SDFS to SCLKt Setup Time
5
Full IV 1.0 ns
t
HSF
SDFS to SCLKt Hold Time
5
Full IV 2.0 ns
Serial Frame Output Timing:
t
DSE
SCLKu to SDFE Delay Time Full IV 3.5 11.0 ns
t
SDFEH
SDFE Width High Full V t
SCLK
ns
t
DSO
SCLKu to SDO Delay Time Full IV 4.5 11.0 ns
SCLK Switching Characteristics, SBM = “1”:
t
SCLK
SCLK Period
4
Full I 2 × t
CLK
ns
t
SCLKL
SCLK Width Low Full V 0.5 × t
SCLK
ns
t
SCLKH
SCLK Width High Full V 0.5 × t
SCLK
ns
t
SCLKD
CLK to SCLK Delay Time Full V 6.5 13.0 ns
Serial Frame Timing, SBM = “1”:
t
DSF
SCLKu to SDFS Delay Time Full IV 1.0 4.0 ns
t
SDFSH
SDFS Width High Full V t
SCLK
ns
SCLK Timing Requirements, SBM = “0”:
t
SCLK
SCLK Period Full I 15.4 ns
t
SCLKL
SCLK Width Low Full IV 0.4 × t
SCLK
0.5 × t
SCLK
ns
t
SCLKH
SCLK Width High Full IV 0.4 × t
SCLK
0.5 × t
SCLK
ns
NOTES
1
This specification valid for VDD >= 3.3 V. t
CLKL
and t
CLKH
still apply.
2
Specification pertains to: IN[15:0], EXP[2:0], A/B.
3
Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
4
SCLK period will be ≥ 2 × t
CLK
when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
5
SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
Specifications subject to change without notice.
