PIN # PIN NAME TYPE DESCRIPTION
1 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
2 GND14 PWR Ground pin for 14MHz output and logic.
3 AVDD14 PWR Analog power pin for 14MHz PLL
4 VDD14 PWR Power pin for 14MHz output and logic
5 vREF14_3x/TEST_SEL I/O
14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable
test mode. Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down.
6 GND14 PWR Ground pin for 14MHz output and logic.
7 GNDXTAL PWR Ground pin for Crystal Oscillator.
8 X1_25 IN Crystal input, Nominally 25.00MHz.
9 X2_25 OUT Crystal output, Nominally 25.00MHz.
10 VDDXTAL PWR 3.3V power for the crystal oscillator.
11 GNDPCI PWR Ground pin for PCI outputs and logic.
12 VDDPCI PWR 3.3V power for the PCI outputs and logic
13 PCI4_2x OUT 3.3V PCI clock output
14 PCI3_2x OUT 3.3V PCI clock output
15 PCI2_2x OUT 3.3V PCI clock output
16 PCI1_2x OUT 3.3V PCI clock output
17 PCI0_2x OUT 3.3V PCI clock output
18 GNDPCI PWR Ground pin for PCI outputs and logic.
19 VDDPCI PWR 3.3V power for the PCI outputs and logic
20 VDD48 PWR 3.3V power for the 48MHz output and logic
21 48M_2x OUT 3.3V 48MHz output
22 GND48 PWR Ground pin for 48MHz output and logic.
23 GND96 PWR Ground pin for DOT96 output and logic.
24 DOT96_LPT OUT
True clock of low-power push-pull differential 96MHz output. External series resistors are needed
for termination.
25 DOT96_LPC OUT
Complementary clock of low-power push-pull differential 96MHz output. External series resistors
are needed for termination.
26 AVDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
27 TEST_MODE IN
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test
mode. Refer to Test Clarification Table.
28 CKPWRGD#/PD IN
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power
Up. PD is an asynchronous active high input pin used to put the device into a low power state.
The internal clocks and PLLs are stopped.
29 VDDSRC PWR 3.3V power for the SRC outputs and logic
30 SRC0_LPT OUT
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
31 SRC0_LPC OUT
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
32 GNDSRC PWR Ground pin for SRC outputs and logic.
33 SRC1_LPC OUT
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
34 SRC1_LPT OUT
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
35 SRC2_LPC OUT
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
36 SRC2_LPT OUT
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
37 VDDSRC PWR 3.3V power for the SRC outputs and logic
38 AVDD_SRC PWR 3.3V power for the SRC PLL analog circuits
39 GNDSRC PWR Ground pin for SRC outputs and logic.
40 NC N/A No Connection.
41 NS_SRC0_LPC OUT
Complementary clock of low-power push-pull differential non-spreading SRC output. External
series resistors are needed for termination.
42 NS_SRC0_LPT OUT
