932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS 4
932SQL420 REV 0.8 062012
64MLF Pin Descriptions
PIN # PIN NAME TYPE DESCRIPTION
1 GNDPCI PWR Ground pin for PCI outputs and lo
ic.
2 VDDPCI PWR 3.3V power for the PCI outputs and logic
3 PCI4_2x OUT 3.3V PCI clock output
4 PCI3_2x OUT 3.3V PCI clock output
5 PCI2_2x OUT 3.3V PCI clock output
6 PCI1_2x OUT 3.3V PCI clock output
7 PCI0_2x OUT 3.3V PCI clock output
8 GNDPCI PWR Ground pin for PCI outputs and lo
ic.
9 VDDPCI PWR 3.3V power for the PCI outputs and lo
ic
10 VDD48 PWR 3.3V power for the 48MHz output and logic
11 48M_2x OUT 3.3V 48MHz output
12 GND48 PWR Ground pin for 48MHz output and logic.
13 GND96 PWR Ground pin for DOT96 output and lo
ic.
14 DOT96_LPT OUT
True clock of low-power push-pull differential 96MHz output. External series resistors are needed
for termination.
15 DOT96_LPC OUT
Complementary clock of low-power push-pull differential 96MHz output. External series resistors
are needed for termination.
16 AVDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
17 TEST_MODE IN
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test
mode. Refer to Test Clarification Table.
18 CKPWRGD#/PD IN
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power
Up. PD is an asynchronous active high input pin used to put the device into a low power state.
The internal clocks and PLLs are stopped.
19 VDDSRC PWR 3.3V power for the SRC outputs and lo
ic
20 SRC0_LPT OUT
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
21 SRC0_LPC OUT
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
22 GNDSRC PWR Ground pin for SRC outputs and lo
ic.
23 SRC1_LPC OUT
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
24 SRC1_LPT OUT
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
25 SRC2_LPC OUT
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
26 SRC2_LPT OUT
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
27 VDDSRC PWR 3.3V power for the SRC outputs and lo
ic
28 AVDD_SRC PWR 3.3V power for the SRC PLL analog circuits
29 GNDSRC PWR Ground pin for SRC outputs and lo
ic.
30 NC N/A No Connection.
31 NS_SRC0_LPC OUT
Complementary clock of low-power push-pull differential non-spreading SRC output. External
series resistors are needed for termination.
True clock of low-power push-pull differential non-spreading SRC output. External series resistors
are needed for termination.
33 NS_SRC1_LPC OUT
Complementary clock of low-power push-pull differential non-spreading SRC output. External
series resistors are needed for termination.
34 NS_SRC1_LPT OUT
True clock of low-power push-pull differential non-spreading SRC output. External series resistors
are needed for termination.
35 VDDNS PWR 3.3V power for the Non-Spreading differential outputs outputs and logic
36 GNDNS PWR Ground pin for non-spreadin
differential outputs and lo
ic.
True clock of low-power push-pull differential non-spreading SAS output. External series resistors
are needed for termination.
