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932SQL420BGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS 13
932SQL420 REV 0.8 062012
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 932SQL420. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Current Consumption
AC Electrical Characteristics–Differential Current Mode Outputs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C
1
Case Temperature Tc 110 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current I
DD3.3OP
All outputs active @100MHz,
C
L
= Full load;
250 mA 1
Powerdown Current
I
DD3.3PDZ
6mA1
1
Guaranteed by design and characterization, not 100% tested in production.
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
DC
Measured differentially, PLL
Mode
45 55 % 1
Skew, Output to Output t
sk3SRC
Across all SRC outputs,
V
T
= 50%
50 ps 1
Skew, Output to Output t
sk3CPU
Across all CPU outputs,
V
T
= 50%
50 ps 1
CPU, SRC, NS_SAS outputs 50 ps 1,3
DOT96 output 250 ps 1,3
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Zo=85
Ω
(differential impedance).
3
Measured from differential waveform
Jitter, Cycle to cycle t
jcyc-cyc
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS 14
932SQL420 REV 0.8 062012
Electrical Characteristics–Input/Supply/Common Parameters
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
T
COM
Commmercial range 0 70 °C 1
Input High Voltage V
IH
Single-ended inputs, except
SMBus, low threshold and tri-
level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except
SMBus, low threshold and tri-
level inputs
GND
- 0.3 0.8 V 1
I
IN
Single-ended inputs,
V
IN
= GND, V
IN
= VDD
-5 5 uA 1
I
INP
Single-ended inputs.
V
IN
= 0 V; Inputs with internal
pull-up resistors
V
IN
= VDD; Inputs with internal
pull-down resistors
-200 200 uA 1
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V 1
Input Frequency F
i
25.00 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 5 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
1.8 ms 1,2
SS Modulation Frequency f
MODIN
Allowable Frequency
(Triangular Modulation)
30 31.5 33 kHz 1
Tdrive_PD# t
DRVPD
Differential output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low
Voltage
V
ILSMB
0.8 V 1
SMBus Input
High Voltage
V
IHSMB
2.1 V
DDSMB
V1
SMBus Output
Low Voltage
V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH +
0.15)
1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL -
0.15)
300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating
frequency
100 kHz 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
Input Current
Capacitance
3
Time from deassertion until outputs are >200 mV
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS 15
932SQL420 REV 0.8 062012
DC Electrical Characteristics–Differential Current Mode Outputs
Electrical Characteristics–48MHz
T
A
= T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate dV/dt Scope avera
g
in
g
on 1 4
V/ns
1, 2, 3
Slew rate matching
ΔdV/dt
Slew rate matching, Scope
averaging on
20
%
1, 2, 4
Rise/Fall Time Matching
Δ
Trf
Rise/fall matching, Scope
avera
g
in
g
off
125
ps
1, 8, 9
Voltage High VHigh 660 850 1
Voltage Low VLow -150 150 1
Max Voltage Vmax 1150 1, 7
Min Voltage Vmin -300 1, 7
Vswing Vswing Scope averaging off 300 mV 1, 2
Crossin
g
Volta
g
e (abs) Vcross_abs Scope avera
g
in
g
off 250 550 mV 1, 5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 140 mV 1, 6
2
Measured from differential waveform
7
Includes overshoot and undershoot.
8
Measured from single-ended waveform
9
Measured with scope averaging off, using statistics function. Variation is difference between min and max.
Statistical measurement on
single-ended signal using
oscilloscope math function.
(Scope avera
g
in
g
on)
mV
Measurement on single ended
signal using absolute value.
mV
1
Guaranteed by design and characterization, not 100% tested in production. Z
O
=85
Ω
(differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window
around differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered
on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage
thresholds the oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential
rising edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max
(V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than
T
A
= 0 - 70°C; Supply Voltage V
DD/
V
DDA
= 3.3 V +/-5%,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
NOTES
Output Impedance R
DSP
V
O
= V
D
D
*(0.5) 20 60
Ω
1
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.55 V 1
MIN @V
OH
= 1.0 V -29 mA 1
MAX @V
OH
= 3.135 V -33 mA 1
MIN @V
OL
= 1.95 V 29 mA 1
MAX @ V
OL
= 0.4 V 27 mA 1
Clock High Time T
HIGH
1.5V 8.094 10.036
ns
1
Clock Low Time T
LOW
1.5V 7.694 9.836 ns
1
Edge Rate t
slewr/f_USB
Rising/Falling edge rate 1 2 V/ns 1,2
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T
= 1.5 V
350 ps 1
See "Power Supply and Test Loads" page for termination circuits
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured between 0.8V and 2.0V
Output High Current I
OH
Output Low Current I
OL
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

932SQL420BGLF

Mfr. #:
Buy 932SQL420BGLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK420BQ LOW POWER
Lifecycle:
New from this manufacturer.
Delivery:
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