932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS 16
932SQL420 REV 0.8 062012
Electrical Characteristics–Phase Jitter Parameters
Electrical Characteristics–PCI
T
A
= 0 - 70°C; Supply Voltage V
DD/
V
DDA
= 3.3 V +/-5%,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
hPCIeG1
PCIe Gen 1 86 ps (p-p) 1,2,3,6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(rms)
1,2,6
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR =
10MHz)
1
ps
(rms)
1,2,4,6
QPI & SMI
(100MHz, 4.8Gb/s, 6.4Gb/s
12UI)
0.5
ps
(rms)
1,5,7
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
(rms)
1,5,7
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.2
ps
(rms)
1,5,7
t
jphSAS12G
SAS 12G 1.3
ps
(rms)
1,5,8
1
Guaranteed by desi
n and characterization, not 100% tested in production.
6
Applied to SRC outputs
7
Applies to CPU outputs
8
Applies to NS_SAS, NS_SRC outputs, Spread Off
Phase Jitter
t
jphPCIeG2
t
jphQPI_SMI
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final radification by PCI SIG.
5
Calculated from Intel-supplied Clock Jitter Tool v 1.6.6
T
A
= 0 - 70°C; Supply Voltage V
DD/
V
DDA
= 3.3 V +/-5%,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
NOTES
DSP
O
DD
*(0.5) 12 55
Ω
1
Output High Voltage V
OH
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
OL
OH
OH
= 3.135 V -33 mA 1
MIN @V
OL
OL
= 0.4 V 38 mA 1
Clock High Time T
HIGH
1.5V 12
ns
1
Clock Low Time T
LOW
slewr/f
Rising/Falling edge rate 1 4 V/ns 1,2
Duty Cycle d
t1
T
= 1.5 V 45 55 % 1
Group Skew t
skew
T
= 1.5 V 500 ps 1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T
= 1.5 V
500 ps 1
See "Power Supply and Test Loads" page for termination circuits
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured between 0.8V and 2.0V
Output High Current I
OH
Output Low Current I
OL
