932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS 10
932SQL420 REV 0.8 062012
General SMBus Serial Interface Information for 932SQL420
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
D2
(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Read Address Write Address
D3
(H)
D2
(H)
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
D2
(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
D3
(H)
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS 11
932SQL420 REV 0.8 062012
NOTE: Pin numbers refer to TSSOP
SMBus Table: Output Enable Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
DOT96 Enable Output Enable RW Disable-Low/Low Enable 1
Bit 6
NS_SAS1 Enable Output Enable RW Disable-Low/Low Enable 1
Bit 5
NS_SAS0 Enable Output Enable RW Disable-Low/Low Enable 1
Bit 4
NS_SRC1 Enable Output Enable RW Disable-Low/Low Enable 1
Bit 3
NS_SRC0 Enable Output Enable RW Disable-Low/Low Enable 1
Bit 2
SRC2 Enable Output Enable RW Disable-Low/Low Enable 1
Bit 1
SRC1 Enable Output Enable RW Disable-Low/Low Enable 1
Bit 0
SRC0 Enable Output Enable RW Disable-Low/Low Enable 1
SMBus Table: Output Enable Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
REF14_3x Enable Output Enable RW Disable-Low Enable 1
Bit 6
0
Bit 5
0
Bit 4
CPU3 Output Enable RW Disable-Low/Low Enable 1
Bit 3
CPU2 Output Enable RW Disable-Low/Low Enable 1
Bit 2
CPU1 Output Enable RW Disable-Low/Low Enable 1
Bit 1
CPU0 Output Enable RW Disable-Low/Low Enable 1
Bit 0
Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0
SMBus Table: Output Enable Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
0
Bit 6
0
Bit 5
PCI4 Enable Output Enable RW Disable-Low Enable 1
Bit 4
PCI3 Enable Output Enable RW Disable-Low Enable 1
Bit 3
PCI2 Enable Output Enable RW Disable-Low Enable 1
Bit 2
PCI1 Enable Output Enable RW Disable-Low Enable 1
Bit 1
PCI0 Enable Output Enable RW Disable-Low Enable 1
Bit 0
48MHz Enable Output Enable RW Disable-Low Enable 1
SMBus Table: Differential Amplitude Control
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
CPU AMPLITUDE 1 RW 00 = 700mV 01 = 800mV 0
Bit 6
CPU AMPLITUDE 0 RW 10 = 900mV 11 = 1000mV 1
Bit 5
SRC AMPLITUDE 1 RW 00 = 700mV 01 = 800mV 0
Bit 4
SRC AMPLITUDE 0 RW 10 = 900mV 11 = 1000mV 1
Bit 3
DOT96 AMPLITUDE 1 RW 00 = 700mV 01 = 800mV 0
Bit 2
DOT96 AMPLITUDE 0 RW 10 = 900mV 11 = 1000mV 1
Bit 1
NS-SAS/SRC AMPLITUDE 1 RW 00 = 700mV 01 = 800mV 0
Bit 0
NS-SAS/SRC AMPLITUDE 0 RW 10 = 900mV 11 = 1000mV 1
SMBus Table: Spread Amount Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
SS AMOUNT[1] RW 00= -0.2% 10= -0.4% 1
Bit 0
SS AMOUNT[0] RW 01= -0.3% 11= -0.5% 1
Spread Amount (note
B1b0 must be set to '1')
CPU Vhigh
SRC Vhigh
DOT96 Vhigh
NS-SAS/SRC Vhigh
RESERVED
RESERVED
RESERVED
13
CPU/SRC/
PCI
B
y
te 2
B
y
te 3
16
17
21
62/61
14
54/53
B
y
te 0
24/25
48/47
44/43
50/49
36/35
56/55
34/33
5
30/31
B
y
te 1
60/59
42/41
15
B
y
te 4
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS 12
932SQL420 REV 0.8 062012
SMBus Table: NS_SAS/NS_SRC Frequency Margining Table
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
FS3 Freq. Sel 3 RW 0
Bit 2
FS2 Freq. Sel 2 RW 1
Bit 1
FS1 Freq. Sel 1 RW 1
Bit 0
FS0 Freq. Sel 0 RW 1
SMBus Table: Test Mode and CPU/SRC/PCI Frequency Select Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
Test Mode Test Mode Type RW Hi-Z REF/N 0
Bit 6
Test Select Select Test Mode RW Disable Enable 0
Bit 5
0
Bit 4
1
Bit 3
0
Bit 2
FS2 Freq. Sel 2 RW 0
Bit 1
FS1 Freq. Sel 1 RW 1
Bit 0
FS0 Freq. Sel 0 RW 1
Note: Internal Pull up on 100M_133M# pin will result in default CPU frequency of 100 MHz.
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function Type 0 1 Default
Bit 7
RID3
R
0
Bit 6
RID2
R
0
Bit 5
RID1
R
0
Bit 4
RID0
R
1
Bit 3
VID3
R
0
Bit 2
VID2
R
0
Bit 1
VID1
R
0
Bit 0
VID0
R
1
SMBus Table: Byte Count Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
BC7 RW 0
Bit 6
BC6 RW 0
Bit 5
BC5 RW 0
Bit 4
BC4 RW 0
Bit 3
BC3 RW 1
Bit 2
BC2 RW 0
Bit 1
BC1 RW 1
Bit 0
BC0 RW 0
SMBus Table: Device ID Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
DID7
R
--0
Bit 6
DID6
R
--1
Bit 5
DID5
R
--0
Bit 4
DID4
R
--0
Bit 3
DID3
R
--0
Bit 2
DID2
R
--0
Bit 1
DID1
R
--1
Bit 0
DID0
R
--0
RESERVED
Device ID
(42 hex)
Byte Count
Programming b(7:0)
Writing to this register will configure
how many bytes will be read back,
default is A bytes.
(0 to 9
-
-
-
-
-
Byte 7
-
-
-
-
-
-
-
-
-
-
-
B
y
te 9
B
y
te 5
B
y
te 6
-
RESERVED
-
-
-
-
-
-
-
RESERVED
RESERVED
-
-
REVISION ID
(1h forB rev)
B
y
te 8
-
-
RESERVED
See NS_SAS/NS_SRC Frequency
Table.
RESERVED
1 for B rev
0001 for ICS/IDTVENDOR ID
See CPU/SRC/PCI Frequency
Select Table
RESERVED

932SQL420BGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK420BQ LOW POWER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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