P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 19 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.2.8 Dual data pointers
The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1
determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is
selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data
pointers can be accomplished by a single INC instruction on AUXR1 (see Figure 6).
Fig 5. Internal and external data memory structure
000H
2FFH
00H
FFH
UPPER 128 B
INTERNAL RAM
LOWER 128 B
INTERNAL RAM
(INDIRECT AND
DIRECT
ADDRESSING)
(INDIRECT
ADDRESSING)
(DIRECT
ADDRESSING)
SPECIAL
FUNCTION
REGISTERS (SFRs)
80H
FFH
FFFFH
000H
EXTERNAL
DATA
MEMORY
EXTERNAL
DATA
MEMORY
2FFH
0000H
EXTRAM = 0 EXTRAM = 1
EXPANDED RAM
0300H
(INDIRECT
ADDRESSING)
(INDIRECT
ADDRESSING)
(INDIRECT
ADDRESSING)
FFFFH
80H
7FH
002aaa517
EXPANDED
RAM
768 B
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 20 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.3 Flash memory IAP
6.3.1 Flash organization
The P89LV51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP
capability, in a second 8 kB block, is provided to allow the user code to be programmed
in-circuit through the serial port. There are three methods of erasing or programming of
the flash memory that may be used. First, the flash may be programmed or erased in the
end-user application by calling low-level routines through a common entry point (IAP).
Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn, call
low-level routines through the same common entry point that can be used by the end-user
application. Third, the flash may be programmed or erased using the parallel method by
using a commercially available EPROM programmer which supports this device.
6.3.2 Boot block (block 1)
When the microcontroller programs its own flash memory, all of the low level details are
handled by code that is contained in block 1. A user program calls the common entry point
in the block 1 with appropriate parameters to accomplish the desired operation. Boot block
operations include erase user code, program user code, program security bits, etc.
Fig 6. Dual data pointer organization
Table 10. AUXR1 - Auxiliary register 1 (address A2H) bit allocation
Not bit addressable; reset value 00H.
Bit 7 6 5 4 3 2 1 0
Symbol ----GF20-DPS
Table 11. AUXR1 - Auxiliary register 1 (address A2H) bit descriptions
Bit Symbol Description
7 to 4 - Reserved for future use. Should be set to ‘0’ by user programs.
3 GF2 General purpose user-defined flag.
2 0 This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
1 - Reserved for future use. Should be set to ‘0’ by user programs.
0 DPS Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
DPL
82H
DPS = 0 DPTR0
DPS = 1 DPTR1
external data memory
DPS
002aaa518
DPH
83H
DPTR0
DPTR1
AUXR1 / bit0
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 21 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
A chip-erase operation can be performed using a commercially available parallel
programer. This operation will erase the contents of this boot block and it will be
necessary for the user to reprogram this boot block (block 1) with the NXP-provided
ISP/IAP code in order to use the ISP or IAP capabilities of this device. Go to
http://www.nxp.com/support for questions or to obtain the hex file for this device.
6.3.3 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LV51RB2/RC2/RD2 through the serial port. This
firmware is provided by NXP and embedded within each P89LV51RB2/RC2/RD2 device.
The NXP ISP facility has made in-circuit programming in an embedded application
possible with a minimum of additional expense in components and circuit board area. The
ISP function uses five pins (V
DD
, V
SS
, TXD, RXD, and RST). Only a small connector
needs to be available to interface your application to an external circuit in order to use this
feature.
6.3.4 Using ISP
The ISP feature allows for a wide range of baud rates to be used in your application,
independent of the oscillator frequency. It is also adaptable to a wide range of oscillator
frequencies. This is accomplished by measuring the bit-time of a single bit in a received
character. This information is then used to program the baud rate in terms of timer counts
based on the oscillator frequency. The ISP feature requires that an initial character (an
uppercase U) be sent to the P89LV51RB2/RC2/RD2 to establish the baud rate. The ISP
firmware provides auto-echo of received characters. Once baud rate initialization has
been performed, the ISP firmware will only accept Intel Hex-type records. Intel Hex
records consist of ASCII characters used to represent hexadecimal values and are
summarized below:
:NNAAAARRDD..DDCC<crlf>
In the Intel Hex record, the ‘NN’ represents the number of data bytes in the record. The
P89LV51RB2/RC2/RD2 will accept up to 32 data bytes. The ‘AAAA’ string represents the
address of the first byte in the record. If there are zero bytes in the record, this field is often
set to 0000. The ‘RR’ string indicates the record type. A record type of ‘00’ is a data
record. A record type of ‘01’ indicates the end-of-file mark. In this application, additional
record types will be added to indicate either commands or data for the ISP facility.
The maximum number of data bytes in a record is limited to 32 (decimal). ISP commands
are summarized in Table 12. As a record is received by the P89LV51RB2/RC2/RD2, the
information in the record is stored internally and a checksum calculation is performed. The
operation indicated by the record type is not performed until the entire record has been
received. Should an error occur in the checksum, the P89LV51RB2/RC2/RD2 will send an
‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to
match the checksum in the record, then the command will be executed. In most cases,
successful reception of the record will be indicated by transmitting a ‘.’ character out the
serial port.

P89LV51RD2BN,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 40DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union