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P89LV51RD2BN,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P76
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 28 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Table 15. TMOD - Timer/counter mode control register (address 89H) bit descriptions
Bit Symbol Description
T1/T0 Bits controlling Timer1/Timer0
GATE Gating control when set. Timer/counter ‘x’ is enabled only while ‘INTx’
INTx pin is HIGH and ‘TRx’ control pin is set. When cleared, Timer ‘x’
is enabled whenever ‘TRx’ control bit is set.
C/
T Gating Timer or Counter Selector cleared for Timer operation (input
from internal system clock). Set for Counter operation (input from ‘Tx’
input pin).
Table 16. TMOD - Timer/counter mode control register (address 89H) M1/M0 operating
mode
M1 M0 Operating mode
0 0 0 8048 timer ‘TLx’ serves as 5-bit prescaler
0 1 1 16-bit Timer/counter ‘THx’ and ‘TLx' are cascaded; there
is no prescaler.
1 0 2 8-bit auto-reload Timer/counter ‘THx’ holds a value which
is to be reloaded into ‘TLx’ each time it overflows.
1 1 3 (Timer 0) TL0 is an 8-bit Timer/counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only
controlled by Timer 1 control bits.
1 1 3 (Timer 1) Timer/counter 1 stopped.
Table 17. TCON - Timer/counter control register (address 88H) bit allocation
Bit addressable; reset value: 0000 0000B; reset source(s): any reset.
Bit 7 6 5 4 3 2 1 0
Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Table 18. TCON - Timer/counter control register (address 88H) bit descriptions
Bit Symbol Description
7 TF1 Timer 1 overflow flag. Set by hardware on Timer/counter overflow.
Cleared by hardware when the processor vectors to Timer 1 Interrupt
routine, or by software.
6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/counter 1
on/off.
5 TF0 Timer 0 overflow flag. Set by hardware on Timer/counter overflow.
Cleared by hardware when the processor vectors to Timer 0 Interrupt
routine, or by software.
4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/counter 0
on/off.
3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 29 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.4.1 Mode 0
Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit
counter with a fixed divide-by-32 prescaler. Figure 7 shows mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either GATE = 0 or INTn = 1. Setting GATE = 1 allows the Timer
to be controlled by external input INTn, to facilitate pulse width measurements. TRn is a
control bit in the Special Function Register TCON (Figure 6). The GATE bit is in the TMOD
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 7). There are two
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
6.4.2 Mode 1
Mode 1 is the same as mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See Figure 8.
2 IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 1.
1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 0.
Table 18. TCON - Timer/counter control register (address 88H) bit descriptions
…continued
Bit Symbol Description
Fig 7. Timer/counter 0 or 1 in mode 0 (13-bit counter)
002aaa519
osc/6
Tn pin
TRn
TnGate
INTn pin
C/T = 0
C/T = 1
TLn
(5-bits)
THn
(8-bits)
TFn
control
overflow
interrupt
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 30 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.4.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as
shown in Figure 9. Overflow from TLn not only sets TFn, but also reloads TLn with the
contents of THn, which must be preset by software. The reload leaves THn unchanged.
Mode 2 operation is the same for Timer 0 and Timer 1.
6.4.4 Mode 3
When timer 1 is in mode 3 it is stopped (holds its count). The effect is the same as setting
TR1=0.
Timer 0 in mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for
mode 3 and Timer 0 is shown in Figure 10. TL0 uses the Timer 0 control bits: T0C/T,
T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the
‘Timer 1’ interrupt.
Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in mode
3, the P89LV51RB2/RC2/RD2 can look like it has an additional Timer.
Note: When Timer 0 is in mode 3, Timer 1 can be turned on and off by switching it into
and out of its own mode 3. It can still be used by the serial port as a baud rate generator,
or in any application not requiring an interrupt.
Fig 8. Timer/counter 0 or 1 in mode 1 (16-bit counter)
002aaa520
osc/6
Tn pin
TRn
TnGate
INTn pin
C/T = 0
C/T = 1
TLn
(8-bits)
THn
(8-bits)
TFn
control
overflow
interrupt
Fig 9. Timer/counter 0 or 1 in mode 2 (8-bit auto-reload)
002aaa521
osc/6
Tn pin
TRn
TnGate
INTn pin
TLn
(8-bits)
THn
(8-bits)
TFn
control
overflow
reload
interrupt
C/T = 0
C/T = 1
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P89LV51RD2BN,112

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Buy P89LV51RD2BN,112
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 40DIP
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