P89LV51RD2BN,112 Datasheet P89LV51RB2BA,512, P89LV51RB2BBC,557, P89LV51RC2BN,112 | P58-P60

Product data sheet Rev. 05 — 15 December 2009 58 of 76

NXP Semiconductors

P89LV51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

6.12 Power-saving modes

The device provides two power saving modes of operation for applications where power

consumption is critical. The two modes are Idle and Power-down, see Table 56.

6.12.1 Idle mode

Idle mode is entered by setting the IDL bit in the PCON register. In Idle mode, the Program

Counter (PC) is stopped. The system clock continues to run and all interrupts and

peripherals remain active. The on-chip RAM and the special function registers hold their

data during this mode.

Table 51. IP0H - Interrupt priority 0 high register (address B7H) bit descriptions

Bit Symbol Description

7 - Reserved for future use. Should be set to ‘0’ by user programs.

6 PPCH PCA interrupt priority HIGH bit.

5 PT2H Timer 2 interrupt priority HIGH bit.

4 PSH Serial Port interrupt priority HIGH bit.

3 PT1H Timer 1 interrupt priority HIGH bit.

2 PX1H External interrupt 1 priority HIGH bit.

1 PT0H Timer 0 interrupt priority HIGH bit.

0 PX0H External interrupt 0 priority HIGH bit.

Table 52. IP1 - Interrupt priority 1 register (address F8H) bit allocation

Bit addressable; reset value: 00H.

Bit 7 6 5 4 3 2 1 0

Symbol - - - PBO - - - -

Table 53. IP1 - Interrupt priority 1 register (address F8H) bit descriptions

Bit Symbol Description

7 to 5 - Reserved for future use. Should be set to ‘0’ by user programs.

4 PBO Brownout interrupt priority bit.

3 to 0 - Reserved for future use. Should be set to ‘0’ by user programs.

Table 54. IP1H - Interrupt priority 1 high register (address F7H) bit allocation

Not bit addressable; reset value: 00H.

Bit 7 6 5 4 3 2 1 0

Symbol - - - PBOH - - - -

Table 55. IP1H - Interrupt priority 1 high register (address F7H) bit descriptions

Bit Symbol Description

7 to 5 - Reserved for future use. Should be set to ‘0’ by user programs.

4 PBOH Brownout interrupt priority bit.

3 to 0 - Reserved for future use. Should be set to ‘0’ by user programs.

Product data sheet Rev. 05 — 15 December 2009 59 of 76

NXP Semiconductors

P89LV51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

The device exits Idle mode through either a system interrupt or a hardware reset. When

exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits

Idle mode. After exiting the Interrupt Service Routine, the interrupted program resumes

execution beginning at the instruction immediately following the instruction which invoked

the Idle mode. A hardware reset starts the device similar to a power-on reset.

6.12.2 Power-down mode

The Power-down mode is entered by setting the PD bit in the PCON register. In the

Power-down mode, the clock is stopped and external interrupts are active for level

sensitive interrupts only. SRAM contents are retained during Power-down mode, and the

minimum V

level is 2.0 V.

The device exits Power-down mode through either an enabled external level sensitive

interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits

Power-down. Holding the external interrupt pin low restarts the oscillator, the signal must

hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon

interrupt signal restored to logic V

, the interrupt service routine program execution

resumes beginning at the instruction immediately following the instruction which invoked

Power-down mode. A hardware reset starts the device similar to power-on reset.

To exit properly out of Power-down mode, the reset or external interrupt should not be

executed before the V

line is restored to its normal operating voltage. Be sure to hold

voltage long enough at its normal operating level for the oscillator to restart and

stabilize (normally less than 10 ms).

Table 56. Power-saving modes

Mode Initiated by State of MCU Exited by

Idle mode Software (Set IDL bit in

PCON) MOV PCON, #01H

Clock is running. Interrupts,

serial port and timers/counters

are active. Program Counter is

stopped. ALE and

PSEN

signals are HIGH level during

Idle. All registers remain

unchanged.

Enabled interrupt or hardware reset. Start of

interrupt clears IDL bit and exits Idle mode,

after the ISR (Interrupt Service Routine)

RETI (Return from Interrupt) instruction,

program resumes execution beginning at

the instruction following the one that invoked

Idle mode. A user could consider placing

two or three NOP (No Operation)

instructions after the instruction that invokes

Idle mode to eliminate any problems. A

hardware reset restarts the device similar to

a power-on reset.

Power-down

mode

Software (Set PD bit in

PCON) MOV PCON, #02H

Clock is stopped. On-chip

SRAM and SFR data is

maintained. ALE and

PSEN

signals are LOW level during

power-down. External

Interrupts are only active for

level sensitive interrupts, if

enabled.

Enabled external level sensitive interrupt or

hardware reset. Start of interrupt clears PD

bit and exits Power-down mode, after the

ISR RETI instruction program resumes

execution beginning at the instruction

following the one that invoked Power-down

mode. A user could consider placing two or

three NOP instructions after the instruction

that invokes Power-down mode to eliminate

any problems. A hardware reset restarts the

device similar to a power-on reset.

Product data sheet Rev. 05 — 15 December 2009 60 of 76

NXP Semiconductors

P89LV51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

6.13 System clock and clock options

6.13.1 Clock input options and recommended capacitor values for oscillator

Shown in Figure 27 are the input and output (XTAL1, XTAL2) of an internal inverting

ampliﬁer, which can be conﬁgured for use as an on-chip oscillator.

When driving the device from an external clock source, XTAL2 should be left disconnected

and XTAL1 should be driven.

At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to

interaction between the ampliﬁer and its feedback capacitance. However, the capacitance

will not exceed 15 pF once the external signal meets the V

and V

speciﬁcations.

Crystal manufacturer, supply voltage, and other factors may cause circuit performance to

differ from one application to another. C1 and C2 should be adjusted appropriately for

each design. Table 57 shows the typical values for C1 and C2 vs. crystal type for various

frequencies.

More speciﬁc information about on-chip oscillator design can be found in the

FlashFlex51

Oscillator Circuit Design Considerations

application note.

6.13.2 Clock doubling option

By default, the device runs at 12 clocks per machine cycle (X1 mode). The device has a

clock doubling option to speed up to 6 clocks per machine cycle (see Table 58). Clock

double mode can be enabled either by an external programmer or using IAP. When set,

the EDC bit in FST register will indicate 6-clock mode.

The clock double mode is only for doubling the internal system clock and the internal ﬂash

memory, i.e. EA = 1. To access the external memory and the peripheral devices, careful

consideration must be taken. Also note that the crystal output (XTAL2) frequency will not

be doubled.

Table 57. Recommended values for C1 and C2 by crystal type

Crystal C1=C2

Quartz 20 pF to 30 pF

Ceramic 40 pF to 50 pF

On-chip oscillator External clock drive

Fig 27. Oscillator characteristics

002aaa545

XTAL2

XTAL1

002aaa546

XTAL2

n.c.

XTAL1

external

oscillator

signal

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P89LV51RD2BN,112

Mfr. #:

Buy P89LV51RD2BN,112

Manufacturer:

NXP Semiconductors

Description:

IC MCU 8BIT 64KB FLASH 40DIP

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P89LV51RD2BN,112

P89LV51RD2BN,112

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