P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 68 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Table 64. External clock drive
Symbol Parameter Oscillator Unit
12 MHz Variable
Min Max Min Max
f
osc
oscillator frequency - - 0 33 MHz
T
cy(clk)
clock cycle time 83 - - - ns
t
CHCX
clock HIGH time - - 0.35T
cy(clk)
0.65T
cy(clk)
ns
t
CLCX
clock LOW time - - 0.35T
cy(clk)
0.65T
cy(clk)
ns
t
CLCH
clock rise time - 20 - - ns
t
CHCL
clock fall time - 20 - - ns
Fig 32. External clock drive waveform
t
CHCL
t
CLCX
t
CHCX
T
cy(clk)
t
CLCH
002aaa907
Table 65. Serial port timing
Symbol Parameter Oscillator Unit
12 MHz Variable
Min Max Min Max
T
XLXL
serial port clock cycle time 1.0 - 12T
cy(clk)
- µs
t
QVXH
output data set-up to clock rising edge
time
700 - 10T
cy(clk)
− 133 - ns
t
XHQX
output data hold after clock rising
edge time
50 - 2T
cy(clk)
− 50 - ns
t
XHDX
input data hold after clock rising edge
time
0- 0 - ns
t
XHDV
input data valid to clock rising edge
time
- 700 - 10T
cy(clk)
− 133 ns
