P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 57 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Table 45. IEN0 - Interrupt enable register 0 (address A8H) bit descriptions
Bit Symbol Description
7 EA Interrupt Enable Bit: EA = 1 interrupt(s) can be serviced, EA = 0
interrupt servicing disabled.
6 EC PCA Interrupt Enable bit.
5 ET2 Timer 2 Interrupt Enable.
4 ES Serial Port Interrupt Enable.
3 ET1 Timer 1 Overflow Interrupt Enable.
2 EX1 External Interrupt 1 Enable.
1 ET0 Timer 0 Overflow Interrupt Enable.
0 EX0 External Interrupt 0 Enable.
Table 46. IEN1 - Interrupt enable register 1 (address E8H) bit allocation
Bit addressable; reset value: 00H.
Bit 7 6 5 4 3 2 1 0
Symbol - - - - EBO - - -
Table 47. IEN1 - Interrupt enable register 1 (address E8H) bit descriptions
Bit Symbol Description
7 to 4 - Reserved for future use. Should be set to ‘0’ by user programs.
3 EBO Brownout Interrupt Enable. 1 = enable, 0 = disable.
2 to 0 - Reserved for future use. Should be set to ‘0’ by user programs.
Table 48. IP0 - Interrupt priority 0 low register (address B8H) bit allocation
Bit addressable; reset value: 00H.
Bit 7 6 5 4 3 2 1 0
Symbol - PPC PT2 PS PT1 PX1 PT0 PX0
Table 49. IP0 - Interrupt priority 0 low register (address B8H) bit descriptions
Bit Symbol Description
7 - Reserved for future use. Should be set to ‘0’ by user programs.
6 PPC PCA interrupt priority LOW bit.
5 PT2 Timer 2 interrupt priority LOW bit.
4 PS Serial Port interrupt priority LOW bit.
3 PT1 Timer 1 interrupt priority LOW bit.
2 PX1 External interrupt 1 priority LOW bit.
1 PT0 Timer 0 interrupt priority LOW bit.
0 PX0 External interrupt 0 priority LOW bit.
Table 50. IP0H - Interrupt priority 0 high register (address B7H) bit allocation
Not bit addressable; reset value: 00H.
Bit 7 6 5 4 3 2 1 0
Symbol - PPCH PT2H PSH PT1H PX1H PT0H PX0H
