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UJA1162T,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
UJA1162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 10 of 29
NXP Semiconductors
UJA1162
Self-supplied high-speed CAN transceiver with Sleep mode
• V
BUF
< V
uvd(BUF)
OR V
IO
< V
uvd(VIO)
The CAN transceiver switches to CAN Offline mode:
• from CAN Offline Bias mode when the UJA1162 is in Standby or Sleep mode and no
activity has been detected on the bus (no CAN edges) for t > t
to(silence)
OR
• when the UJA1162 switches from Off or Overtemp mode to Standby mode
The CAN transceiver switches from CAN Offline mode to CAN Offline Bias mode if:
• a standard wake-up pattern (according to ISO11898-5) is detected on the CAN bus
OR
• the UJA1162 switches to Normal mode while V
BUF
< V
uvd(BUF)
OR V
IO
< V
uvd(VIO)
6.3.1.3 CAN Off mode
The CAN transceiver is switched off completely with the bus lines floating when:
• the UJA1162 switches to Off or Overtemp mode OR
• V
BAT
falls below the CAN receiver undervoltage detection threshold, V
uvd(CAN)
It will be switched on again on entering CAN Offline mode when V
BAT
rises above the
undervoltage recovery threshold (V
uvr(CAN)
) and the UJA1162 is no longer in Off/Overtemp
mode. CAN Off mode prevents reverse currents flowing from the bus when the battery
supply to the UJA1162 is lost.
6.3.2 CAN standard wake-up
The UJA1162 monitors the bus for a wake-up pattern when the CAN transceiver is in
Offline mode.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be
transmitted on the CAN bus within the wake-up timeout time (t
to(wake)
) to pass the wake-up
filter and trigger a wake-up event (see Figure 4
; note that additional pulses may occur
between the recessive/dominant phases). The recessive and dominant phases must last
at least t
wake(busrec)
and t
wake(busdom)
, respectively.
Pin RXD is driven LOW when a valid CAN wake-up pattern is detected on the bus.
Fig 4. CAN wake-up timing
t
dom
≥ t
wake(busdom)
recessive
t
rec
≥ t
wake(busrec)
t
dom
≥ t
wake(busdom)
dominant dominant
015aaa267
t
wake
< t
to(wake)
CAN wake-up
UJA1162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 11 of 29
NXP Semiconductors
UJA1162
Self-supplied high-speed CAN transceiver with Sleep mode
6.4 WAKE pin
In Standby and Sleep modes, a local wake-up event is triggered by a LOW-to-HIGH or a
HIGH-to-LOW transition on the WAKE pin. In applications that don’t make use of the local
wake-up facility, the WAKE pin should be connected to GND for optimal EMI performance.
Pin RXD is driven LOW when a valid edge is detected on pin WAKE.
6.5 VIO supply pin
Pin VIO should be connected to the microcontroller supply voltage. This will cause the
signal levels on TXD, RXD, SLPN and CTS to be adjusted to the I/O levels of the
microcontroller, enabling direct interfacing without the need for glue logic.
Fig 5. CAN transceiver state machine
DDD
&$1+&$1/WHUPLQDWHG
V
9
%8)
25
XYG&$1
UJA1162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 12 of 29
NXP Semiconductors
UJA1162
Self-supplied high-speed CAN transceiver with Sleep mode
6.6 CAN transceiver status pin (CTS)
Pin CTS is driven HIGH to indicate to microcontroller that the transceiver is fully enabled
and data can be transmitted and received via the TXD/RXD pins.
Pin CTS is actively driven LOW:
• while the transceiver is starting up (e.g. during a transition from Standby to Normal
mode) or
• if pin TXD is clamped LOW for t > t
to(dom)TXD
or
• if an undervoltage is detected on VIO or BUF
6.7 CAN fail-safe features
6.7.1 TXD dominant timeout
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than
the TXD dominant time-out time (t
to(dom)TXD
), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
traffic). The TXD dominant time-out timer is reset when pin TXD goes HIGH. The TXD
dominant time-out time also defines the minimum possible bit rate of 15 kbit/s.
6.7.2 Pull-up on TXD pin
Pin TXD has an internal pull-up (towards V
IO
) to ensure a safe defined recessive driver
state in case the pin is left floating.
6.7.3 Pull-down on SLPN pin
Pin SLPN has an internal pull-down (to GND) to ensure the UJA1162 switches to Sleep
mode if SLPN is left floating.
6.7.4 Loss of power at pin BAT
A loss of power at pin BAT has no impact on the bus lines or on the microcontroller. No
reverse currents flow from the bus.
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UJA1162T,118

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NXP Semiconductors
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IC TRANSCEIVER 14SOIC
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