AT25128N1-10SI-1.8 Datasheet AT25128N-10SI-1.8, AT25128N-10SI-2.7, AT25128T1-10TI-2.7 | P7-P9

AT25128/256

0872O–SEEPR–03/05

WRITE ENABLE (WREN): The device will power-up in the write disable state when V

is applied. All programming instructions must therefore be preceded by a Write Enable

instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write

Disable instruction disables all programming modes. The WRDI instruction is indepen-

dent of the status of the WP

pin.

READ STATUS REGISTER (RDSR): The Read Status Register instruction provides

access to the status register. The Ready/Busy and Write Enable status of the device

can be determined by the RDSR instruction. Similarly, the Block Write Protection bits

indicate the extent of protection

employed. These bits are set by using the WRSR instruc-

tion

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select

one of four levels of protection. The AT25128/256 is divided into four array segments.

Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of

the data within any selected segment will therefore be READ only. The block write pro-

tection levels and corresponding status register control bits are shown in Table 8.

The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties

and functions as the regular memory cells (e.g. WREN, t

, RDSR).

Table 6. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN X X X BP1 BP0 WEN RDY

Table 7. Read Status Register Bit Definition

Bit Definition

Bit 0 (RDY) Bit 0 = “0” (RDY) indicates the device is READY.

Bit 0 = “1” indicates the write cycle is in progress.

Bit 1 (WEN) Bit 1 = “0” indicates the device is not WRITE ENABLED. Bit 1 = 1

indicates the device is WRITE ENABLED.

Bit 2 (BP0) See Table 8.

Bit 3 (BP1) See Table 8.

Bits 4 - 6 are “0”s when device is not in an internal write cycle.

Bit 7 (WPEN) See Table 9.

Bits 0 – 7 are “1”s during an internal write cycle.

Table 8. Block Write Protect Bits

Level

Status Register Bits Array Addresses Protected

BP1 BP0 AT25128 AT25256

0 0 0 None None

1(1/4) 0 1 3000 - 3FFF 6000 - 7FFF

2(1/2) 1 0 2000 - 3FFF 4000 - 7FFF

3(All) 1 1 0000 - 3FFF 0000 - 7FFF

AT25128/256

0872O–SEEPR–03/05

The WRSR instruction also allows the user to enable or disable the write protect (WP)

pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is

enabled when the WP

pin is low and the WPEN bit is “1”. Hardware write protection is

disabled when either the WP

pin is high or the WPEN bit is “0.” When the device is hard-

ware write protected, writes to the Status Register, including the Block Protect bits and

the WPEN bit, and the block-protected sections in the memory array are disabled.

Writes are only allowed to sections of the memory which are not block-protected.

NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to

“0”, as long as the WP

pin is held low.

READ SEQUENCE (READ): Reading the AT25128/256 via the SO pin requires the

following sequence. After the CS

line is pulled low to select a device, the READ op-code

is transmitted via the SI line followed by the byte address to be read (see Table 10 on

page 9). Upon completion, any data on the SI line will be ignored. The data (D7

– D0) at

the specified address is then shifted out onto the SO line. If only one byte is to be read,

the CS

line should be driven high after the data comes out. The read sequence can be

continued since the byte address is automatically incremented and data will continue to

be shifted out. When the highest address is reached, the address counter will roll over to

the lowest address allowing the entire memory to be read in one continuous read cycle.

WRITE SEQUENCE (WRITE): In order to program the AT25128/256, two separate

instructions must be executed. First, the device must be write enabled via the WREN

instruction. Then a Write instruction may be executed. Also, the address of the memory

location(s) to be programmed must be outside the protected address field location

selected by the block write protection level. During an internal write cycle, all commands

will be ignored except the RDSR instruction.

A Write instruction requires the following sequence. After the CS

line is pulled low to

select the device, the Write op-code is transmitted via the SI line followed by the byte

address and the data (D7

– D0) to be programmed (see Table 10 on page 9). Program-

ming will start after the CS

pin is brought high. The low-to-high transition of the CS pin

must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.

The Ready/Busy status of the device can be determined by initiating a Read Status

the write cycle has ended. Only the RDSR instruction is enabled during the write pro-

gramming cycle.

Table 9. WPEN Operation

WPEN WP WEN

Protected

Blocks

Unprotected

Blocks

Status

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected

X High 1 Protected Writable Writable

AT25128/256

0872O–SEEPR–03/05

The AT25128/256 is capable of a 64-byte page write operation. After each byte of data

is received, the six-low order address bits are internally incremented by one; the high-

order bits of the address will remain constant. If more than 64 bytes of data are transmit-

ted, the address counter will roll over and the previously written data will be overwritten.

The AT25128/256 is automatically returned to the write disable state at the completion

of a write cycle.

NOTE: If the device is not Write enabled (WREN), the device will ignore the Write

instruction and will return to the standby state, when CS

is brought high. A new CS fall-

ing edge is required to reinitiate the serial communication.

Timing Diagrams (for SPI Mode 0 (0, 0))

Figure 3. Synchronous Data Timing

Table 10. Address Key

Address AT25128 AT25256

- A

Don’t Care Bits A

- A

HI-Z

VALID IN

DIS

SCK

CSH

CSS

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

AT25128N1-10SI-1.8

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AT25128N1-10SI-1.8

AT25128N1-10SI-1.8

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