1©2016 Integrated Device Technology, Inc Revision A February 5, 2016
General Description
The 8S58035I is a high speed 2-to-6 Differential-to-LVPECL Fanout
Buffer. The 8S58035I is optimized for high speed and very low output
skew, making it suitable for use in demanding applications such as
SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel. The
internally terminated differential inputs and V
REF_AC
pins allow other
differential signal families such as LVDS, LVHSTL and CML to be
easily interfaced to the input with minimal use of external compo-
nents. The device also has a 2:1 MUX input, allowing for easy selec-
tion between two clock reference sources. The 8S58035I is
packaged in a small 5mm x 5mm 32-pin VFQFN package which
makes it ideal for use in space-constrained applications.
Features
• Six LVPECL outputs
• INx, nINx inputs can accept the following differential input levels:
LVPECL, LVDS, CML
• 50 internal input termination to V
T
• Two selectable differential input pairs
• Maximum output frequency: 3.2GHz
• Output Skew: 45ps (maximum)
• Part-to-Part Skew: 200ps (maximum)
• Additive phase jitter, RMS: 47fs (typical),
(f
REF
= 622.08MHz, 12kHz - 20MHz, V
CC
= 3.3V)
• Propagation Delay: 580ps (maximum)
• LVPECL mode operating voltage supply range:
V
CC
= 2.5V±5%, 3.3V±10%, V
EE
= 0V
• -40°C to 85°C ambient operating temperature
8S58035I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm Epad Size
K Package
Top View
Pin Assignment
9 10111213 14 15 16
32 31 302928 27 26 25
V
EE
SEL
V
CC
Q0
nQ0
Q1
nQ1
V
CC
V
EE
nc
V
CC
nQ5
Q5
nQ4
Q4
V
CC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
IN0
V
T0
V
REF_AC0
nIN0
IN1
V
T1
V
REF_AC1
nIN1
V
EE
V
CC
Q2
nQ2
Q3
nQ3
V
CC
V
EE
Block Diagram
IN0
nIN0
Q0
nQ0
V
T0
Q1
nQ1
Q2
nQ2
Q3
nQ3
IN1
nIN1
V
T1
V
REF_
AC
1
Q4
nQ4
Q5
nQ5
0
1
SEL
Pullup
V
REF_
AC
0
50
50
50
50
8S58035I
Data Sheet
Low Skew, 2:1 LVPECL MUX with 1:6
Fanout and Internal Termination