13©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Termination for 2.5V LVPECL Outputs
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50 to V
CC
– 2V. For V
CC
= 2.5V, the V
CC
– 2V is very close to
ground level. The R3 in Figure 6B can be eliminated and the
termination is shown in Figure 6C.
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6C. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
2.5V
50
Ω
50
Ω
R1
250
Ω
R3
250
Ω
R2
62.5
Ω
R4
62.5
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
R3
18
Ω
+
14©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the
footprint of the package corresponding to the exposed metal pad
or exposed heat slug on the package, as shown in Figure 7. The
solderable area on the PCB, as defined by the solder mask,
should be at least the same size/shape as the exposed pad/slug
area on the package to maximize the thermal/electrical
performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges
of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering
process which may result in voids in solder between the exposed
pad/slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the
Application Note on the Surface Mount Assembly of Amkor’s
Thermally/ Electrically Enhance Leadframe Base Package, Amkor
Technology.
Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
15©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8S58035I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8S58035I is the sum of the core power plus the output power dissipated due to loading.
The following is the power dissipation for V
CC
= 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating output power dissipated due to loading.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.6V * 90mA = 324mW
Power (outputs)
MAX
= 32.35mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 32.35mW = 194.1mW
Power Dissipation for internal termination R
T
Power (R
T
)
MAX
= 2 * [(V
IN_MAX
)
2
/ (2 * R
T_MIN
)] = 2 * [(1.4V)
2
/ (2 * 40)] = 49mW
Total Power_
MAX
(3.6V, with all outputs switching) = 324mW + 194.1mW + 49mW= 567.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that
the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.567W * 42.7°C/W = 109°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board.
Table 6. Thermal Resistance
JA
for 32 Lead VFQFN, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 42.7°C/W 37.3°C/W 33.5°C/W

8S58035AKILF

Mfr. #:
Manufacturer:
Description:
Clock Drivers & Distribution 2:1 MUX WITH 6 OUTPUT FANOUT BUFFER
Lifecycle:
New from this manufacturer.
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