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8S58035AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
4©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Table 4C. Differential DC Characteristics, V
CC
= 2.375V to 3.6V, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing diagram.
NOTE 2: Guaranteed by design.
NOTE 3: Because of the internal termination R
IN
, the input current I
IN
will be determined by the voltages applied at INx, nINx and V
Tx
.
Observe the voltages applied to those pins so the input current does not exceed the maximum limit.
Table 4D. LVPECL DC Characteristics, V
CC
= 2.375V to 3.6V, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50 to V
CC
– 2V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
R
DIFF_IN
Differential
Input Resistance
IN0-to-nIN0
or
IN1-to-nIN1
80 100 120
R
IN
Input Resistance
INx-to-V
TX
or
nINx-to-V
TX
40 50 60
V
IH
Input High
Voltage
IN0, nIN0,
IN1, nIN1
1.2 V
CC
V
V
IL
Input Low Voltage
IN0, nIN0,
IN1, nIN1
0V
IH
– 0.15 V
V
IN
Input Voltage Swing; NOTE 1 0.15 1.4 V
V
DIFF_IN
Differential Input Voltage Swing 0.3 2.8 V
I
IN
Input Current;
NOTE 2, 3
IN0, nIN0,
IN1, nIN1
45 mA
V
REF_AC
Bias Voltage
V
REF_AC0
or
V
REF_AC1
V
CC
- 1.4 V
CC
– 1.3 V
CC
– 1.2 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE1 V
CC
- 1.05 V
CC
- 0.85 V
V
OL
Output Low Voltage; NOTE 1 V
CC
- 1.9 V
CC
- 1.6 V
V
OUT
Output Voltage Swing 0.55 1.0 mV
V
DIFF_OUT
Differential Output Voltage Swing 1.1 2.0 V
5©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= 2.375V to 3.6V, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE: All parameters characterized at f
OUT
3.2GHz input signal, unless otherwise noted.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output
differential crosspoints.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 3.2 GHz
t
PD
Propagation Delay;
NOTE 1
INx to Qx 390480580ps
tsk(o) Output Skew; NOTE 2, 4 45 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 200 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
section
622.08MHz,
Integration Range:
12kHz to 20MHz
47 fs
t
R
/ t
F
Output Rise/Fall Time 20% - 80% 40 160 ps
6©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the
fundamental frequency to the power value of the fundamental.
This ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the required
offset is specified, the phase noise is called a dBc value, which
simply means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
have issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
Measured using a Rohde & Schwarz SMA100A as the input
source.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 47fs (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

8S58035AKILF

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Clock Drivers & Distribution 2:1 MUX WITH 6 OUTPUT FANOUT BUFFER
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