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8S58035AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
16©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 7.
Figure 7. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination
voltage
of V
CC
– 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.85V
(V
CC_MAX
– V
OH_MAX
) = 0.85V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.6V
(V
CC_MAX
– V
OL_MAX
) = 1.6V
Pd_H is the power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.85V)/50] * 0.85V = 19.55mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L]
* (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.6V)/50] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.35mW
V
OUT
V
CC
V
CC
-
2V
Q1
RL
17©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Reliability Information
Table 7.
JA
vs. Air Flow Table for a 32 Lead VFQFN
Transistor Count
The transistor count for 8S58035I: 348
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 42.7°C/W 37.3°C/W 33.5°C/W
18©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
32 Lead VFQFN Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
Table 8. Package Dimensions
NOTE: This package mechanical drawing is a generic drawing that
applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device.
The pin count and pinout are shown on the front page. The
package dimensions are in Table 8.
Reference Document: JEDEC Publication 95, MO-220
To p View
Index Area
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singula tion
A
0. 08 C
C
A3
A1
S eating Plan e
E2
E2
2
L
(N
-1)x e
(R ef.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N & N
Odd
1
2
e
2
(Ty p.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Th er mal
Base
N
OR
Anvil
Singulation
N-1N
CHAMFER
1
2
N-1
1
2
N
RADIUS
4
4
Bottom View w/Type C IDBottom View w/Type A ID
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N 32
A 0.80 1.00
A1 00.05
A3 0.25 Ref.
b 0.18 0.25 0.30
N
D
& N
E
8
D & E 5.00 Basic
D2 & E2 3.0 3.3
e 0.50 Basic
L 0.30 0.40 0.50
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

8S58035AKILF

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Clock Drivers & Distribution 2:1 MUX WITH 6 OUTPUT FANOUT BUFFER
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