7©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Parameter Measurement Information
Output Load Test Circuit
Propagation Delay
Part-to-Part Skew
Single-ended & Differential Input/Output Swing
Output Skew
Output Rise/Fall Time
SCOPE
Qx
nQx
V
EE
V
CC
2V
-0.375V to -1.6V
t
PD
nQ[0:5]
Q[0:5]
IN[0:1]
nIN[0:1]
tsk(pp)
Part 1
Part 2
Qx
nQx
Qy
nQy
V
IN
, V
OUT
V
DIFF_IN
, V
DIFF_OUT
Qx
nQx
Qy
nQy
nQ[0:5]
Q[0:5]
8©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept
single ended levels. The reference voltage V
1
= V
CC
/2 is
generated by the bias resistors R1 and R2. The bypass capacitor
(C1) is used to help filter noise on the DC bias. This bias circuit
should be located as close to the input pin as possible. The ratio
of R1 and R2 might need to be adjusted to position the V
1
in the
center of the input voltage swing. For example, if the input clock
swing is 2.5V and V
CC
= 3.3V, R1 and R2 value should be
adjusted to set V
1
at 1.25V. The values below are for when both
the single ended swing and V
CC
are at the same voltage. This
configuration requires that the sum of the output impedance of the
driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
IL
cannot be less
than -0.3V and V
IH
cannot be more than V
CC
+ 0.3V. Though
some of the recommended components might not be used, the
pads should be placed in the layout. They can be utilized for
debugging purposes. The datasheet specifications are
characterized and guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
9©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
3.3V Differential Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both signals must meet the V
IN
and V
IH
input requirements. Figures 2A to 2D show interface
examples for the IN/nIN input with built-in 50 terminations driven
by the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor, use
their termination recommendation. Please consult with the vendor
of the driver component to confirm the driver termination
requirements.
Figure 2A. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Figure 2C. IN/nIN Input with Built-In 50
Driven by a CML Driver with Open Collector
Figure 2B. IN/nIN Input with Built-In 50
Driven by an LVPECL Driver
Figure 2D. IN/nIN Input with Built-In 50
Driven by a CML Driver with Built-In 50
Pullup
C1
C2
VT
V_REF_AC
50Ω
50Ω
3.3V CML with
Built-In Pullup
3.3V
IN
nIN
3.3V
Receiver with
Built-In 50Ω
Zo = 50Ω
Zo = 50Ω

8S58035AKILF

Mfr. #:
Manufacturer:
Description:
Clock Drivers & Distribution 2:1 MUX WITH 6 OUTPUT FANOUT BUFFER
Lifecycle:
New from this manufacturer.
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