Two Selectable Inputs, 8 LVPECL Outputs,
SiGe Clock Fanout Buffer
Data Sheet
ADCLK948
Rev. B Document Feedback
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FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK948 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
V
REF
x pin is available for biasing ac-coupled inputs.
The ADCLK948 features eight full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias V
CC
to the positive supply and V
EE
to ground. For ECL
operation, bias V
CC
to ground and V
EE
to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to V
CC
− 2 V for a total differential
output swing of 1.6 V.
The ADCLK948 is available in a 32-lead LFCSP and specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
V
T
0
V
REF
0
V
REF
1
IN_SEL
CLK0
CLK0
V
T
1
CLK1
CLK1
LVPECL
ADCLK948
REFERENCE
REFERENCE
08280-001
Figure 1.
