ADCLK948BCPZ Datasheet ADCLK948BCPZ, ADCLK948BCPZ-REEL7 | P7-P9

ADCLK948 Data Sheet

Rev. B | Page 6 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. NC = NO CONNECT.

2. THE EPAD MUST BE SOLDERED TO THE V

EE

POWER PLANE.

CLK0

V

REF

0

V

T

0

CLK1

V

T

1

V

REF

1

Q2

Q3

Q4

Q5

NC

V

CC

Q7

Q6

V

CC

V

CC

IN_SEL

V

CC

Q0

Q1

V

CC

V

CC

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

1

12

13

14

15

16

32

31

30

29

28

27

26

25

ADCLK948

T

OP

VIEW

(Not to Scale)

08280-002

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK0 Differential Input (Positive) 0.

2

CLK0

Differential Input (Negative) 0.

3 V

REF

0 Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and

CLK0

inputs.

4 V

T

0 Center Tap. Center tap of a 100 Ω input resistor for CLK0 and

CLK0

inputs.

5 CLK1 Differential Input (Positive) 1.

6

CLK1

Differential Input (Negative) 1.

7 V

T

1 Center Tap. Center tap of a 100 Ω input resistor for CLK1 and

CLK1

inputs.

8 V

REF

1 Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and

CLK1

inputs.

9 NC No Connection.

10, 15, 16, 25, 26, 31 V

CC

Positive Supply Pin.

11, 12

Q7

, Q7 Differential LVPECL Outputs.

13, 14

Q6

, Q6 Differential LVPECL Outputs.

17, 18

Q5

, Q5 Differential LVPECL Outputs.

19, 20

Q4

, Q4 Differential LVPECL Outputs.

21, 22

Q3

, Q3 Differential LVPECL Outputs.

23, 24

Q2

, Q2 Differential LVPECL Outputs.

27, 28

Q1

, Q1 Differential LVPECL Outputs.

29, 30

Q0

, Q0

Differential LVPECL Outputs.

32 IN_SEL Input Select. Logic 0 selects CLK0 and

CLK0

inputs. Logic 1 selects CLK1 and

CLK1

inputs.

EPAD Exposed Pad. The EPAD must be soldered to the V

EE

power plane.

Data Sheet ADCLK948

Rev. B | Page 7 of 12

TYPICAL PERFORMANCE CHARACTERISTICS

V

CC

= 3.3 V, V

EE

= 0 V, V

ICM

= V

REF

x, T

A

= 25°C, clock outputs terminated at 50 Ω to V

CC

− 2 V, unless otherwise noted.

C3

C4

C3

100mV/DIV 500ps/DIV

08280-003

Figure 3. LVPECL Output Waveform @ 200 MHz

1.8

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

0 1000 2000 3000 4000 5000

DIFFERENTIAL OUTPUT VOLTAGE (V)

FREQUENCY (MHz)

08280-004

Figure 4. Differential Output Voltage vs. Frequency, V

ID

> 1.1 V p-p

225

180

185

190

195

200

205

210

215

220

01.81.61.41.21.00.80.60.40.2

PROPAGATION DELAY (ps)

DIFFERENTIAL INPUT VOLTAGE SWING (V)

08280-005

Figure 5. Propagation Delay vs. Differential Input Voltage

C4

C3

C4

100mV/DIV 100ps/DIV

08280-006

Figure 6. LVPECL Output Waveform @ 1000 MHz

214

213

212

211

210

209

208

207

–40 806040200–20

PROPAGATION DELAY (ps)

TEMPERATURE (°C)

08280-007

Figure 7. Propagation Delay vs. Temperature, V

ID

= 1.6 V p-p

230

190

200

210

220

0.9 3.12.92.72.52.32.11.91.71.51.31.1

PROPAGATION DELAY (ps)

DC COMMON-MODE VOLTAGE (V)

+85°C

+25°C

–40°C

08280-008

Figure 8. Propagation Delay vs. DC Common-Mode Voltage vs. Temperature,

Input Slew Rate > 25 V/ns

ADCLK948 Data Sheet

Rev. B | Page 8 of 12

1.56

1.54

1.52

1.50

1.48

1.46

1.44

1.42

2.75

2.85

2.95

3.05

3.15

3.25 3.35

3.45 3.55 3.65 3.75

DIFFERENTIAL OUTPUT VOLTAGE SWING (V)

POWER SUPPLY (V)

+85°C

+25°C

–40°C

08280-009

Figure 9. Differential Output Voltage Swing vs. Power Supply Voltage vs.

Temperature, V

ID

= 1.6 V p-p

08280-010

350

300

250

200

150

100

50

0

2.75

3.753.50

3.253.00

SUPPLY CURRENT (mA)

SUPPLY VOLTAGE (V)

ICC

IEE

+85°C

+25°C

–40°C

Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature,

All Outputs Loaded (50 Ω to V

CC

− 2 V).

–90

–170

–160

–150

–140

–130

–120

–110

–100

10

100 1k 10k 100k 1M 10M 100M

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

CLOCK SOURCE

ADCLK948

ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT

E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A

WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672),

WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A

WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D).

08280-011

Figure 11. Absolute Phase Noise Measured @1 GHz

300

250

200

150

100

50

0

0 252015105

RANDOM JITTER (f

S

rms)

INPUT SLEW RATE (V/ns)

08280-012

Figure 12. RMS Random Jitter vs. Input Slew Rate, V

ID

Method

ADCLK948BCPZ

ADCLK948BCPZ

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