ADCLK948BCPZ Datasheet ADCLK948BCPZ, ADCLK948BCPZ-REEL7 | P4-P6

Data Sheet ADCLK948

Rev. B | Page 3 of 12

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Typical (Typ column) values are given for V

− V

= 3.3 V and T

= 25°C, unless otherwise noted. Minimum (Min column) and maximum

(Max column) values are given over the full V

− V

= 3.3 V ± 10% and T

= −40°C to +85°C variation, unless otherwise noted.

Table 1. Clock Inputs and Outputs

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC INPUT CHARACTERISTICS

Input Common Mode Voltage V

ICM

+ 1.5 V

− 0.1 V

Input Differential Range V

0.4 3.4 V p-p ±1.7 V between input pins

Input Capacitance C

0.4 pF

Input Resistance

Single-Ended Mode 50 Ω

Differential Mode 100 Ω

Common Mode 50 kΩ Open V

Input Bias Current 20 µA

Hysteresis 10 mV

DC OUTPUT CHARACTERISTICS

Output Voltage High Level V

− 1.26 V

− 0.76 V 50 Ω to (V

− 2.0 V)

Output Voltage Low Level V

− 1.99 V

− 1.54 V 50 Ω to (V

− 2.0 V)

Output Voltage, Single Ended V

610 960 mV V

− V

, output static

Reference Voltage V

REF

Output Voltage (V

+ 1)/2 V −500 µA to +500 µA

Output Resistance 235 Ω

Table 2. Timing Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

AC PERFORMANCE

Maximum Output Frequency 4.5 4.8 GHz See Figure 4 for differential output voltage vs.

frequency, >0.8 V differential output swing

Output Rise Time t

40 75 90 ps 20% to 80% measured differentially

Output Fall Time t

40 75 90 ps

Propagation Delay t

175 210 245 ps V

ICM

= 2 V, V

= 1.6 V p-p

Temperature Coefficient 50 fs/°C

Output-to-Output Skew

9 25 ps

Part-to-Part Skew 45 ps V

= 1.6 V p-p

Additive Time Jitter

Integrated Random Jitter 28 fs rms BW = 12 kHz − 20 MHz, CLK = 1 GHz

Broadband Random Jitter

75 fs rms V

= 1.6 V p-p, 8 V/ns, V

ICM

= 2 V

Crosstalk-Induced Jitter

90 fs rms

CLOCK OUTPUT PHASE NOISE

Absolute Phase Noise

Input slew rate > 1 V/ns (see Figure 11,

the phase noise plot, for more details)

= 1 GHz −119 dBc/Hz @100 Hz offset

−134 dBc/Hz @1 kHz offset

−145 dBc/Hz @10 kHz offset

−150 dBc/Hz @100 kHz offset

−150 dBc/Hz >1 MHz offset

The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.

This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.

ADCLK948 Data Sheet

Rev. B | Page 4 of 12

Table 3. Input Select Control Pin

Parameter Symbol Min Typ Max Unit

Logic 1 Voltage V

− 0.4 V

Logic 0 Voltage V

1 V

Logic 1 Current I

100 μA

Logic 0 Current I

0.6 mA

Capacitance 2 pF

Table 4. Power

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Supply Voltage Requirement V

− V

2.97 3.63 V 3.3 V + 10%

Power Supply Current Static

Negative Supply Current I

VEE

96 120 mA V

− V

= 3.3 V ± 10%

Positive Supply Current I

VCC

288 330 mA V

− V

= 3.3 V ± 10%

Power Supply Rejection

PSR

VCC

<3 ps/V V

− V

= 3.3 V ± 10%

Output Swing Supply Rejection

PSR

VCC

28 dB V

− V

= 3.3 V ± 10%

Change in t

per change in V

Change in output swing per change in V

Data Sheet ADCLK948

Rev. B | Page 5 of 12

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Supply Voltage

− V

6 V

Input Voltage

CLK0, CLK1,

CLK0

CLK1

, IN_SEL V

− 0.5 V to

+ 0.5 V

CLK0, CLK1,

CLK0

CLK1

to V

x Pin (CML,

LVPECL Termination)

±40 mA

CLK0, CLK1 to

CLK0

CLK1

±1.8 V

Input Termination, V

x to CLK0, CLK1,

CLK0

and

CLK1

±2 V

Maximum Voltage on Output Pins V

+ 0.5 V

Maximum Output Current 35 mA

Voltage Reference (V

REF

x) V

to V

Operating Temperature Range

Ambient −40°C to +85°C

Junction 150°C

Storage Temperature Range −65°C to +150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

DETERMINING JUNCTION TEMPERATURE

To determine the junction temperature on the application

printed circuit board (PCB), use the following equation:

= T

CASE

+ (Ψ

× P

)

where:

is the junction temperature (°C).

CASE

is the case temperature (°C) measured by the customer at

the top center of the package.

is from Table 6.

is the power dissipation.

Values of θ

are provided for package comparison and PCB

design considerations. θ

can be used for a first-order approxi-

mation of T

by the equation

= T

+ (

× P

)

where T

is the ambient temperature (°C).

Values of θ

are provided in Table 6 for package comparison

and PCB design considerations.

ESD CAUTION

THERMAL PERFORMANCE

Table 6.

Parameter Symbol Description Value

Unit

Junction-to-Ambient Thermal Resistance

Still Air Per JEDEC JESD51-2

0 m/sec Air Flow 49.8 °C/W

Moving Air

JMA

Per JEDEC JESD51-6

1 m/sec Air Flow 43.5 °C/W

2.5 m/sec Air Flow

39.0

°C/W

Junction-to-Board Thermal Resistance

Moving Air Per JEDEC JESD51-8

1 m/sec Air Flow 30.7 °C/W

Junction-to-Case Thermal Resistance

Moving Air Per MIL-STD 883, Method 1012.1

Die-to-Heatsink 8.8 °C/W

Junction-to-Top-of-Package Characterization Parameter

Still Air Per JEDEC JESD51-2

0 m/sec Air Flow 0.7 °C/W

Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the

application to determine if they are similar to those assumed in these calculations.

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ADCLK948BCPZ

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Description:

Clock Buffer 8 LVPECL Outpts SiGe

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ADCLK948BCPZ

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