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NOIL1SM0300A-QDC

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10
Global Shutter
In a global shutter light integration takes place on all
pixels in parallel, although subsequent readout is sequential.
Figure 10 shows the integration and read out sequence for
the synchronous shutter. All pixels are light sensitive at the
same period of time. The whole pixel core is reset
simultaneously and after the integration time all pixel values
are sampled together on the storage node inside each pixel.
The pixel core is read out line by line after integration. Note
that the integration and read out cycle can occur in parallel
or in sequential mode.
Figure 10. Synchronous Shutter Operation
Time axis
Line number
Integration time Burst Readout time
COMMON RESET
COMMON SAMPLE&HOLD
Flash could occur here
Non Destructive Readout (NDR)
Figure 11. Principle of Non Destructive Readout
[1]
time
The sensor can also be read out in a non destructive way.
After a pixel is initially reset, it can be read multiple times,
without resetting. The initial reset level and all intermediate
signals can be recorded. High light levels saturate the pixels
quickly, but a useful signal is obtained from the early
samples. For low light levels, one has to use the later or latest
samples. Essentially an active pixel array is read multiple
times, and reset only once. The external system intelligence
takes care of the interpretation of the data. Table 11
summarizes the advantages and disadvantages of non
destructive readout.
NOTE 1:This mode can be activated by setting the NDR SPI register. The NDR SPI register must only be changed during FOT. The NDR
bit should be set high during the first Frame Overhead Time after the pixel array is reset; the NDR bit must be set low during the last
Frame Overhead Time before the pixel array is being reset.
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Table 11. ADVANTAGES AND DISADVANTAGES OF NON DESTRUCTIVE READOUT
Advantages Disadvantages
Low noise because it is a true CDS. System memory required to record the reset level and the interme-
diate samples.
High sensitivity because the conversion capacitance is kept rather
low.
Requires multiples readings of each pixel, thus higher data
throughput.
High dynamic range because the results includes signal for short
and long integrations times.
Requires system level digital calculations.
Sequencer
The sequencer generates the complete internal timing of
the pixel array and the readout. The timing can be controlled
by the user through the SPI register settings. The sequencer
operates on the same clock as the ADCs. This is a division
by 4 of the input clock.
Table 12 shows a list of the internal registers with a short
description. In the next section, the registers are explained
in more detail.
Table 12. INTERNAL REGISTERS
Address Bits Name Description
0 (0000)
10:0 SEQUENCER Default <10:0>: 00000101001
1 mastermode 1: master mode; 0: slave mode
1 ss 1: ss in y; 0: no subsampling
2 gran clock granularity
1 enable_analog_out 1: enabled; 0: disabled
1 calib_line 1: line calibration; 0 frame calibration
1 res2_en 1: enable DS; 0: Disable DS
1 res3_en 1: enable TS; 0: Disable TS
1 reverse_x 1: readout in reverse x direction
0: readout in normal x direction
1 reverse_y 1: readout in reverse y direction
0: readout in normal y direction
1 Ndr 1: enable non destructive readout
0: disable non destructive readout
1 (0001) 7:0 START_X Start pointer X readout
Default <7:0>: 00000000
2 (0010) 8:0 START_Y Start pointer Y readout
Default <8:0>: 000000000
3 (0011) 7:0 NB_PIX Number of kernels to read out (4 pixel kernel)
Default <7:0>: 10100000
4 (0100) 11:0 RES1_LENGTH Length of reset pulse (in number of lines)
Default <11:0>: 000000000010
5 (0101) 11:0 RES2_TIMER Position of reset DS pulse in number of lines
Default <11:0>: 000000000000
6 (0110) 11:0 RES3_TIMER Position of reset TS pulse in number of lines
Default <11:0>: 000000000000
7(0111) 11:0 FT_TIMER Position of frame transfer in number of lines
Default <11:0>: 000111100001
8 (1000) 7:0 VCAL DAC input for vcal
Default <7:0>: 01001010
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Table 12. INTERNAL REGISTERS
Address DescriptionNameBits
9 (1001) 7:0 VBLACK DAC input for vblack
Default <7:0>: 01101011
10 (1010) 7:0 VOFFSET DAC input for voffset
Default <7:0>: 01010101
11 (1011)
11:0 ANA_IN_ADC Activate analog ADC input
Default <11:0>: 000011110000
4 sel_test_path Selection of analog test path
4 sel_path Selection of normal analog path
4 bypass_mux Bypass of digital 4 to 1 mux
12 (1100) 11:0 PGA_SETTING PGA settings
Default <11:0>: 111110110000
4 gain_pga Gain settings PGA
1 unity_pga PGA unity amplification
1 sel_uni Preamplification of 0.5 (0: enabled)
1 enable_analog_in Activate analog input
4 enable_adc Put separate ADCs in standby
1 sel_calib_fast Select fast calibration of PGA
13 (1101) 11:0 CALIB_ADC <11:0>
Calibration word of the ADCs
Default:
calib_adc<11:0>:101011011111
calib_adc<23:12>:011011011011
calib_adc<32:24>:000011011011
14 (1110) 11:0 CALIB_ADC <23:12>
15 (1111) 8:0 CALIB_ADC <32:24>
Detailed Description of the Internal Registers
The registers should only be changed during FOT (when
frame valid is low).
These registers should only be changed during RESET_N
is low:
• Mastermode register
• Granularity register
Sequencer Register <10:0>
The sequencer register is an 11 bit wide register that
controls all of the sequencer settings. It contains several
”sub-registers”.
Mastermode (1 bit)
This bit controls the selection of mastermode/slavemode.
The sequencer can operate in two modes: master mode and
slave mode. In master mode all the internal timing is
controlled by the sequencer, based on the SPI settings. In
slave mode the integration timing is directly controlled over
three pins, the readout timing is still controlled by the
sequencer.
1: Master mode (default)
0: Slave mode
Subsampling (1bit)
This bit enables/disables the subsampling mode.
Subsampling is only possible in Y direction and follows this
pattern:
• Read one, skip one: Y0Y0Y0Y0…
By default, the subsampling mode is disabled.
Clock granularity (2 bits)
The system clock (80 MHz) is divided several times on
chip.
The clock, that drives the ”snapshot” or synchronous
shutter sequencer, can be programmed using the granularity
register. The value of this register depends on the speed of
your system clock.
11: > 80 MHz
10: 40-80 MHz (default)
01: 20-40 MHz
00: < 20 MHz
Enable analog out (1 bit)
This bit enables/disables the analog output amplifier.
1: enabled
0: disabled (default)
Calib_line (1bit)
This bit sets the calibration method of the PGA. Different
calibration modes can be set, at the beginning of the frame
and for every subsequent line that is read.
1: Calibration is done every line (default)
0: Calibration is done every frame (less row fixed pattern
noise)
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NOIL1SM0300A-QDC

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ON Semiconductor
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Image Sensors LUPA300 MONO LLC48
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